Vertically staggered bondpad array

Details Vertically staggered bondpad array Vertically staggered bondpad array

2005-01-25

2005-01-25

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Configuration or pattern of bonds

C257S773000, C257S738000, C257S700000, C257S692000, C257S690000

Reexamination Certificate

active

06847123

ABSTRACT:
A silicon device which includes a silicon substrate and a bond pad array on the silicon substrate which is configured to be conductively connected to bond wire. The bond pad array consists of a plurality of bond pads which are vertically staggered on the silicon substrate. The vertical staggering allows the bond pads to be packed closer together on the silicon substrate, thereby reducing the horizontal space which is consumed by the bond pads on the silicon substrate, and thereby resulting in a reduction in die size. Preferably, the bond pads are also horizontally staggered on the silicon substrate, thereby allowing the bond pads to be spaced even closer together.

REFERENCES:
patent: 5627408 (1997-05-01), Kusumi
patent: 5734559 (1998-03-01), Banerjee et al.
patent: 6214638 (2001-04-01), Banerjee
patent: 6329827 (2001-12-01), Beaman et al.
patent: 6661101 (2003-12-01), Hiraga

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