Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Outside periphery of package having specified shape or...
Reexamination Certificate
1997-12-31
2002-01-29
Clark, Jhihan B. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Outside periphery of package having specified shape or...
C257S685000, C257S686000, C257S678000
Reexamination Certificate
active
06342731
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to vertically mountable semiconductor devices and devices which orient semiconductor devices perpendicularly relative to a carrier substrate. In particular, this invention relates to vertical surface mount package assemblies and alignment devices for biasing leads of the semiconductor device against terminals on a carrier substrate to establish and maintain electrical communication therebetween. The present invention also relates to vertical surface mount packages with low impedance and to user-upgradable, vertical surface mount package assemblies.
2. Background of Related Art
Vertical surface mount packages are known in the art. When compared with traditional, horizontally mountable semiconductor packages and horizontally oriented multi-chip packages, many vertical surface mount packages have a superior ability to transfer heat. Vertical surface mount packages also consume less area on a carrier substrate than a horizontally mounted package of the same size. Thus, many skilled individuals in the semiconductor industry are finding vertical surface mount packages more desirable than their traditional, horizontally mountable counterparts.
Exemplary vertical surface mount packages are disclosed in the following U.S. Pat. Nos.: Re. 34,794 (the “'794 patent”), issued to Warren M. Farnworth on Nov. 22, 1994; U.S. Pat. No. 5,444,304 (the “'304 patent”), issued to Kouija Hara and Jun Tanabe on Aug. 22, 1995; U.S. Pat. No. 5,450,289, issued to Young D. Kweon and Min C. An on Sep. 12, 1995; U.S. Pat. No. 5,451,815, issued to Norio Taniguchi et al. on Sep. 19, 1995; U.S. Pat. No. 5,592,019, issued to Tetsuya Ueda et al. on Jan. 7, 1997; and U.S. Pat. No. 5,635,760, issued to Toru Ishikawa on Jun. 3, 1997.
The '794 patent discloses a vertical surface mount package having a gull-wing, zig-zag, in-line lead configuration and a mechanism for mounting the package to a printed circuit board (PCB) or other carrier substrate. The force with which the package mounts to the carrier substrate establishes a tight interference contact between the package's leads and their corresponding terminals on the carrier substrate.
The '304 patent describes a vertical surface mount package which has integrally formed fins radiating therefrom. The fins of that device facilitate the dissipation of heat away from the device. The semiconductor device is electrically connected to the package's leads by wire bonding. The leads of that vertical surface mount package, which extend therefrom in an in-line configuration, are mountable to the terminals of a carrier substrate by soldering.
However, many of the vertical surface mount packages in the prior art are somewhat undesirable from the standpoint that they permanently attach to a carrier substrate. Thus, those vertical surface mount packages are not readily user-upgradable. Moreover, many prior art vertical surface mount packages include relatively long leads, which tend to increase the independance of the leads and reduce the overall speed of systems of which they are a part. Similarly, the wire bonding typically used in many vertical surface mount packages increases the impedance and reduces the overall speed of such devices. As the speed of operation of semiconductor devices increases, more heat is generated by the semiconductor device, requiring greater heat transfer. Similarly, as the speed of operation of semiconductor devices increases, it is important to decrease the length of the leads regarding circuitry connecting the semiconductor device to other components and thereby decrease the impedance of the leads to increase the responsiveness of the semiconductor device.
Vertical surface mount package sockets are also known in the art. Vertical surface mount package sockets support one or more vertical surface mount packages relative to a carrier substrate. Exemplary devices are disclosed in U.S. Pat. No. 5,619,067 (the “'067 patent”), which issued to Goh J. Sua and Chan M. Yu on Apr. 8, 1997 and U.S. Pat. No. 5,644,161 (the “'161 patent”), which issued to Carmen D. Burns on Jul. 1, 1997. The '161 patent does not describe the platform shown therein in any detail.
The '067 patent discloses a mechanism for vertically mounting a plurality of vertical surface mount packages onto a carrier substrate. A plurality of vertical surface mount packages is installed upside-down within a cover, and against one another in a side-by-side arrangement. The cover is then inverted and attached to the carrier substrate. Clips on each side of the cover insert through and engage an edge of holes formed through the carrier substrate. The downward force of the cover on the vertical surface mount packages forces the leads against the corresponding contacts on the carrier substrate, creating electrical contact therebetween.
The cover of the '067 patent is somewhat undesirable for several reasons. First, the vertical surface mount packages illustrated by that patent have conventional, long, bent leads. Such long leads tend to increase the impedance of such vertical surface mount packages. Second, the cover, as described, includes no mechanism for aligning the devices so that the corresponding leads and carrier substrate contacts match up to each other. The only alignment mechanism described by the '067 patent includes the two clips on the cover and the corresponding crude holes formed through the carrier substrate. Further, in order to effectively position the vertical surface mount packages and maintain adequate electrical contact between the vertical surface mount packages and the carrier substrate, the cover device of the '067 patent must be filled to capacity with vertical surface mount packages. The illustrated clip-hole attachment mechanism also seems inadequate for establishing and maintaining an adequate interference contact between the vertical surface mount package leads and the carrier substrate contacts.
What is needed is a low impedance, vertical surface mount package which is readily removable from and reinstallable upon a carrier substrate. A vertical surface mount package alignment and attachment device which transfers heat away from the vertical surface mount package and establishes and maintains adequate electrical connections between a vertical surface mount package and a carrier substrate is also needed.
SUMMARY OF THE INVENTION
The vertically mountable semiconductor device assembly of the present invention includes very short stub contacts, which impart it with low impedance. The assembly of the present invention includes an alignment device, which exerts consistent downward force upon all of the vertically mountable semiconductor devices disposed therein to establish and maintain an electrical connection between the vertically mountable semiconductor device(s) and the carrier substrate. Vertically mountable semiconductor devices are readily removable from and reinstallable in the alignment device, making the device user-upgradable.
An embodiment of the system of the present invention includes a vertically mountable semiconductor device and an alignment device which attaches the vertically mountable semiconductor device to a carrier substrate. The alignment device of the present invention includes one or more receptacles formed therethrough, each of which receives and aligns at least one vertically mountable semiconductor device. The alignment device also includes a mechanism, which is referred to as a contact element, for biasing the vertically mountable semiconductor device(s) disposed within the receptacle(s) against the carrier substrate. A preferred contact element is a cover which exerts constant force on the vertically mountable semiconductor device to establish and maintain a connection with a carrier substrate. A preferred engagement mechanism releasably engages the vertically mountable semiconductor device(s) that has been inserted into the alignment device receptacle(s).
In use, the alignment device is mounted
Farnworth Warren M.
Kinsman Larry D.
Moden Walter L.
Clark Jhihan B.
Micro)n Technology, Inc.
TraskBritt
LandOfFree
Vertically mountable semiconductor device, assembly, and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Vertically mountable semiconductor device, assembly, and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Vertically mountable semiconductor device, assembly, and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2836166