Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-04-06
2001-04-10
Ngô ;, Ngâ ;n V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S331000, C257S332000, C257S333000, C257S343000, C257S401000
Reexamination Certificate
active
06215150
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to semiconductor device, and in particular, to a vertical MOS semiconductor device where the source, channel and drain thereof are perpendicularly arranged on an SOI substrate. This invention also relates to a method of manufacturing such a vertical MOS semiconductor device.
As a semiconductor device for realizing an increased integration and an increased high speed performance, a MOS semiconductor device which is formed on an SOI (Semiconductor On Insulator) has been known.
FIG. 6
shows a MOS semiconductor device of lateral structure wherein an element substrate (P-type Si)
22
is superimposed via an SiO
2
insulating layer
21
on a supporting substrate
20
of P-type Si. A source
23
, a channel
24
and a drain
25
are respectively formed in this element substrate
22
, and a gate electrode
27
is formed over the channel
24
with a gate insulating layer
26
being interposed therebetween.
FIG. 7
shows a semiconductor device of vertical structure which is disclosed in Japanese Patent Unexamined Publication H/5-41521 and wherein a supporting substrate
28
is superimposed on an element substrate
29
in which a drain
30
, a channel
31
and a source
32
are arranged vertically, i.e. in a direction perpendicular to the element substrate
29
. A gate electrode
34
is arranged beside these regions
30
,
31
and
32
with a gate insulating layer
33
being interposed therebetween. The gate electrode
34
, the drain
30
, the channel
31
and the source
32
are electrically isolated by an insulating layer
35
formed around them. In this
FIG. 7
, reference numeral
36
denotes a source wiring, while
37
denotes a gate wiring and
38
denotes a drain wiring.
The SOI structure shown in
FIG. 6
is advantageous in the respect of achieving an increased high-speed of performance, since the electric field in the inversion layer is weakened in the direction perpendicular to the surface of substrate, thereby making it possible to enhance the mobility of carriers. However, since the source
23
, channel
24
and drain
25
are arranged laterally in this MOS structure, it is accompanied with a problem that the integration degree of elements would be limited.
In the case of the conventional semiconductor device of vertical structure shown in
FIG. 7
, there are also problems that, since the element substrate
29
is designed to be superimposed on the supporting substrate
28
, the manufacturing process thereof becomes complicated thus increasing the manufacturing cost, and at the same time, a parasitic bipolar transistor of P-N-P constituted by the element substrate (P)
29
, the supporting substrate (P)
28
and the drain wiring (N)
38
is caused to be formed, in addition to the essential MOS transistor constituted by the source (N)
32
, the channel (P)
31
and the drain (N)
30
, thus instabilizing the performance of the resultant semiconductor device.
BRIEF SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a vertical semiconductor device, which makes it possible to enhance the integration degree, to simplify the manufacturing method thereof, and to obtain a stabilized performance.
Another object of the present invention is to provide a method of manufacturing such a vertical semiconductor device.
With a view to achieve the above objects, the present invention provides a semiconductor device, which is characterized in that a drain region, a channel region and a source region are vertically formed in a region of a silicon substrate which is encircles by an element isolation film formed one upon another vertically in the silicon substrate; that a drain (or source) electrode and a gate electrode are lead out from said drain (or source) region to a surface of said silicon substrate; and that said gate electrode is electrically isolated by a gate-insulating film, while said drain (or source) electrode is electrically isolated by an insulating film.
Furthermore, as a specific embodiment of the aforementioned semiconductor device, the semiconductor device is characterized in that the drain electrode, channel electrode and source electrode are arranged such that one of the electrodes is disposed at a center and surrounded dually by the remaining two electrodes. In this embodiment, it is also possible to form element isolation films each radially extending from the electrode disposed at the center to the outermost electrode so as to form a plurality of transistors each partitioned by said element isolation films.
The method of manufacturing the aforementioned semiconductor device according to the present invention is characterized in that said method comprises:
a first step wherein a trench is formed in a silicon substrate, and then an element isolation film is formed on an inner surface of said trench;
a second step wherein a drain region, a channel region and a source region are formed so as to be arranged vertically in a region encircled by said element isolation film;
a third step wherein a trench is formed vertically penetrating into a drain region, a channel region and a source region, and then a gate insulating film is formed on an inner surface of said trench;
a fourth step wherein a gate electrode is formed on an inner side portion of said gate insulating film, while a drain electrode (or source electrode) is formed on an outer side portion of said gate insulating film; and
a fifth step wherein an interlayer insulating film is formed between said gate electrode and said drain electrode (or source electrode).
Further, as a specific embodiment of the aforementioned method of manufacturing semiconductor device, the method is characterized in that the second step comprises the steps of:
forming a drain (or source) region by etching said region encircled by the element isolation film at first and then by implanting an impurity in the etched region;
forming a channel region by depositing a non-doped polysilicon in said drain (or source) region at first and then by implanting an impurity in said non-doped polysilicon; and
forming a source (or drain) region by depositing a non-doped polysilicon in said channel region at first and then by implanting an impurity in said non-doped polysilicon.
Furthermore, as another specific embodiment of the aforementioned method, the second step may be performed by a process of ion-implantation to be effected from the top of a region of the silicon substrate which is encircled by said element isolation film, thereby forming said drain region, said channel region and said source region.
Additionally, as another specific embodiment of the aforementioned method, the fourth step may be performed by the steps of;
depositing a polysilicon film on the inner side of gate insulating film; and
performing a doping of said polysilicon film and of a portion of the silicon substrate which is disposed next to said polysilicon film, thereby forming said gate electrode and drain (or source) electrode.
According to the semiconductor device constructed as mentioned above, since the drain region, channel region and source region are vertically disposed on a silicon substrate, the integration degree of elements can be increased, and at the same time, the generation of parasitic bipolar can be prevented, thus making it possible to realize a stabilized performance.
According to the method of manufacturing a semiconductor device mentioned above, it is possible to obtain a semiconductor device which is high in integration density and stable in performance by a simple process comprising the steps of; forming an element isolation film in a silicon substrate thereby to form a region encircled by the element isolation film;performing an ion-implantation of the region encircled by the element isolation film so as to form a drain region, a channel region and a source region, or performing an impurity implantation of the region encircled by the element isolation film after a non-doped polysilicon is deposited on the region so as to form a channel region and source region (or drain region); f
Ngô ; Ngâ ;n V.
Nixon & Vanderhye
Sharp Kabushiki Kaisha
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