Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With electrical contact in hole in semiconductor
Reexamination Certificate
2000-09-15
2001-11-06
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With electrical contact in hole in semiconductor
C257S753000, C257S633000
Reexamination Certificate
active
06313517
ABSTRACT:
The present invention is directed to a method for manufacturing semiconductor components having a specific contact structuring that is provided for a vertical, electrically conductive connection of a plurality of semiconductor components.
BACKGROUND OF THE INVENTION
Semiconductor circuits are currently manufactured in planar technology. The complexity that can be achieved on a chip is limited by the size thereof and by the structural fineness that can be achieved. In conventional technology, the performance of a system composed of a plurality of semiconductor chips connected to one another is significantly limited by the limited number of possible connections between individual chips via terminal contacts, by the low speed of the signal transmission via such connections between various chips, the limited speed in complex chips due to highly branched interconnects and the high power consumption of the interface circuits.
These indicated limitations given the employment of planar technology can be overcome with three-dimensional techniques of the circuitry. The arrangement of a plurality of components above one another allows a parallel communication of these components with little outlay for electrically conductive connections in a level. Moreover, speed-limiting interchip connections are avoided.
A known method for the manufacture of three-dimensional ICs is based on depositing a further semiconductor layer over a level of components and recrystallizing this further semiconductor layer via a suitable method (for example, local heating by laser) and realizing a further component level therein. This technique also exhibits significant limitations that are established by the thermal load on the lower level in the recrystallization and the obtainable yield limited by defects.
In an alternative method, the individual component levels are manufactured separately from one another. These levels are thinned to a few &mgr;m and connected to one another by wafer bonding. The electrical connections are produced in such a way that the individual component levels have their front side and back side provided with contacts for the interchip connection.
U.S. Pat. No. 4,939,568 discloses a vertically integrated semiconductor component and an appertaining manufacturing method, whereby the vertical, conductive connection ensues via vertical metal pins that are located in the substrate of a respective layer level. The manufacturing method provides that the back side of the substrate, which is not provided with a layer structure, be ground down until these vertical conductive connections are uncovered. This side of the substrate can then also be provided with structures. For a direct connection to a following level of the component, the uncovered surfaces of the vertical conductive connections are provided with aluminum contacts.
DE 43 14 907 C1 discloses a manufacturing method for vertically integrated components wherein the component levels are first generated on separate substrates. The two substrates are connected to one another after the application of a planarization layer on the lower substrate and the thinning of the upper substrate. Integrated, pin-shaped metal structures are provided in the substrate for the electrically conductive connection between component levels.
DE 44 00 985 C1 discloses that polyimide be employed for the planarization level, that via holes be generated first for the connection of the component levels and that these be subsequently filled with a contact material. The polyimide layer is disadvantageous in this embodiment, this layer splitting water off during hardening (or, respectively, imidization) and exhibiting a reaction contraction. Water that is split off remains largely in the component and leads to additional stresses that can degrade the finished component in terms of its function or durability. Further, a polyimide layer has only a slight planarization effect of, for example, 30%, so that a plurality of layers are required that in turn exhibit adhesion problems relative to one another.
SUMMARY OF THE INVENTION
A problem of the present invention is to specify an improved structure and a simple manufacturing method for a vertically integrated component and, in particular, to find a suitable material for the intermediate layer that assures a reliable and stress-free connection between the component levels and that withstands further manufacturing steps required for the vertically integrated component without damage.
This object is achieved with a semiconductor component according to the present invention which provides a semiconductor component that comprises a first substrate having an upper surface that is connected to a first component comprising a first contact region that is electrically conductive. The semiconductor component of the present invention also comprises a second substrate also with an upper surface that is connected to a second component that comprises a second contact region that is also electrically conductive. The second substrate further comprises a lower surface and a via hole extending from the upper surface of the second substrate to the lower surface of the second substrate. A connecting layer is sandwiched between the lower surface of the second substrate and the upper surface of the first substrate and a vertical contact structure extends from the second contact region, through the via hole to the first contact region thereby electrically connecting the first contact region to the second contact region thereby electrically connecting the first contact region to the second contact region. The connecting layer comprises a homo-polymerized benzocyclobutene. Manufacturing methods and further advantageous developments of the invention are also disclosed.
The inventive semiconductor component comprises at least two component levels that are respectively realized in their own substrate. In the inventive semiconductor component, the component levels realized in separate substrates are glued by a connecting layer that comprises a homo-polymerized benzocyclobutene (BCB). The electrical connection between the component levels or, respectively, the components realized in the substrates is realized by a vertical contact structure that electrically conductively connects a first contact region on the first substrate to a second contact region on the second substrate.
The invention is the first to propose a structure that enables a stress-free connection of the two substrates. Since the second (upper) substrate is thinned to an optimally low layer thickness of a few &mgr;m before the connecting, this is especially sensitive to thermo-mechanical stresses.
Since only a slight reaction contraction (of, for example, less than 5 percent) occurs when hardening the connecting layer realized with BCB, practically no additional stresses at the boundary surface between connecting layer and second substrate are observed in the inventive semiconductor component.
The connecting layer exhibits a very good adhesion to semiconductors, oxides and metals that usually form the surfaces of semiconductor components. The connecting layer of BCB hardens without splitting off volatile products and exhibits no gas evolution. This is particularly significant given a relatively large-area gluing as in the inventive semiconductor component since such evolution of gasses leads to undesired inclusions of gasses that could in turn lead to additional stresses.
BCB layers are hydrophobic and exhibit no water absorption. They are thermally stable up to approximately 400° C. and therefore withstand standard environmental conditions during further manufacturing steps and during operation of the finished semiconductor component. Added thereto is that BCB layers have a very good planarizing effect. A degree of planarization (DOP) of more than 90 percent can already be achieved with one planarization layer. As a further advantageous property, the inventive connecting layer exhibits an extremely low dielectric constant e of 2.5 (at 1 MHz). As a result thereof, capacitative couplings be
Lauterbach Christl
Weber Werner
Nadav Ori
Schiff & Hardin & Waite
Siemens Aktiengesellshaft
Thomas Tom
LandOfFree
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