Vertically integrated flash EEPROM for greater density and...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S321000

Reexamination Certificate

active

06897520

ABSTRACT:
A nonvolative memory in the form of a flash EEPROM with high density and low cost. A vertical MOS transistor is formed in well etched into a semiconductor substrate, the substrate having a buried layer of doped material of a first conductivity type acting as the channel region. Source and drain regions of this transistor comprise second conductivity type layers doped in the substrate above and below the buried layer. A thin gate oxide or oxide-nitride-oxide (ONO) layer is formed in the well and a floating gate of polysilicon is formed over the gate oxide. A layer of oxide or ONO is formed over the floating gate, and a second polysilicon or metal layer is used to fill the well to form the control gate and word line. A bit line is formed of a layer of metal or polysilicon deposited over an insulating layer on top of the word line and makes contact with the drain of the vertical MOS transistor through a contact window formed adjacent the well.

REFERENCES:
patent: 4964080 (1990-10-01), Tzeng
patent: 5049956 (1991-09-01), Yoshida et al.
patent: 5071782 (1991-12-01), Mori
patent: 5386132 (1995-01-01), Wong
patent: 5572056 (1996-11-01), Hsue et al.
patent: 5589413 (1996-12-01), Sung et al.
patent: 5786612 (1998-07-01), Otani et al.

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