Vertical type transistor and method for fabricating the same

Details Vertical type transistor and method for fabricating the same Vertical type transistor and method for fabricating the same

2005-02-01

2005-02-01

Chen, Kin-Chan (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S201000, C438S700000

Reexamination Certificate

active

06849552

ABSTRACT:
A vertical type transistor and fabricating method therefor. An isolation oxide layer is formed on a field region in a silicon substrate to expose an active region, and an epitaxial silicon layer is formed on the active region of a source region is formed in the vicinity of the surface of the silicon substrate and a drain region is formed on the epitaxial silicon layer. A masking insulator spacer is formed at the side wall of stair part, and the epitaxial silicon layer exposed through the masking insulator spacer is removed. A gate insulating layer is formed along with the exposed surfaces of the epitaxial silicon layer, the source region, and the drain region. A gate electrode is formed to contact with the gate insulating layer. A planarization insulating layer is formed over whole structure, and contact holes and contact plugs are formed thereon.

REFERENCES:
patent: 4786953 (1988-11-01), Morie et al.
patent: 5385852 (1995-01-01), Oppermann et al.
patent: 6239465 (2001-05-01), Nakagawa
patent: 6387758 (2002-05-01), Yu et al.
patent: 6664143 (2003-12-01), Zhang
patent: 6696713 (2004-02-01), Ishibashi

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