Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1994-01-27
1996-08-13
Munson, Gene M.
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257139, H01L 2978, H01L 29739
Patent
active
055459080
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The present invention relates to vertical type insulated-gate semiconductor devices used as power semiconductor elements and a method of producing the same, those of which are suitably employed for integration elements and the like made into unitary configurations together with a signal processing section using a unit thereof or the vertical type insulated-gate semiconductor device as a part thereof.
DESCRIPTION OF RELATED ART
Typical examples of vertical type insulated-gate semiconductor devices include power MOSFETs and insulated- gate bipolar transistors (IGBT) which are characterized by being driven at lower power. The power MOSFET has a rapid switching speed and the IGBT exhibits a lower loss even under a high withstand voltage, both of which features the foregoing and other various properties have widely been utilized in various industrial fields in recent years.
For example, "Nikkei Electronics" published by Nikkei McGraw-Hill Co., May 19, 1986, pp. 1-188 describes that a target of the development and research of the vertical insulated-gate semi-conductor devices is transferred to products with a low withstand voltage and a high withstand voltage, and in particular it mainly describes a vertical type insulated-gate semiconductor device with DMOS type (double diffusion type) based on a planer process exhibiting a high yield point and lower production cost.
Further, this reference teaches a continuous effort intended for reduction of a channel resistance which is a main component of an ON-state resistance with respect to the power MOSFET now mainly under development and research at a withstand voltage of equal to or less than 100 V, and further describes that such reduction has reached an ON-state resistance to an extent of 10 m.OMEGA.. This results from shortening of a channel length, application of a fine machining technique for production of the power MOSFET, and an expansion of a channel width per unit area by an improvement of a cell configuration, and like countermeasures. Moreover, in the IGBT which is mainly under development and research at a stand voltage of equal to or more than 100 V, it is described that an effort is being continued for raising a controllable maximum current value by interrupting a parasitic operation of an NPN transistor that may be a cause of latch-up. The method described includes various approaches; namely, assembling an n.sup.+ -type buffer layer; introduction of a life time killer; and reduction of a voltage drop in a lateral direction within a p-type pinch layer in such a way that a positive hole current flowing into a p-type base layer is decreased by an improvement of the cell configuration; and other like arrangements.
In recent years, less loss and less cost are more in demand by being accompanied with the spread in popularity of the power MOSFETs, however, the channel length shortening due changing a forming condition of the double diffusion layer faces a limit of around 1 .mu.m because of existing problems of the lowered withstand voltage and the increased dispersion, while the reduction of the ON-state resistance obtained by the fine machining technique and the cell shaping improvement reaches a limited state. For example, according to Japanese Patent Application Laid Open SHO-63-266882 (1988), it is widely known that the DMOS type has a minimum point where the ON-state resistance is no longer decreased even by reducing a size of a unit cell by the fine machining technique, and its main cause resides in a sudden increase of a JFET resistance which is a component of the ON-state resistance. A size of the DMOS unit cell, on which the state resistance takes the minimum point, is equal to around 15 .mu.m under the present fine machining technique as disclosed in Japanese Patent Application Laid Open HEI-02-86136 (1990).
On the other hand, less loss and less cost are required more even in the IGBT as is the case of the power MOSFET, the conventional method described above, where the controllable maximum current value is made higher, oft
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T. P. Chow, "Counterdoping of MOS Channel (CDC)--A New Technique of Improving . . . " I.E.E.E. Electron Device letters, Jan. 1988, pp. 28-31.
Wheatley et al.: "COMFET--The Ultimate Poer Device; A General Study of Power Devices" Solid State Technology--Nov. 1985, pp. 121-128 (see appln p. 15).
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A. S. Grove, "Physics and Technology of Semiconductor Devices", John Wiley & Sons, University of California, Berkeley, Calif. 1967, pp. 288, 233.
Okabe Naoto
Tokura Norihiro
Munson Gene M.
Nippondenso Co. Ltd.
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