Vertical transistor and vertical transistor array

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S328000, C257SE27057, C257SE27096

Reexamination Certificate

active

07928490

ABSTRACT:
A vertical transistor including a substrate, a gate, a base line and a gate dielectric layer is provided. The substrate includes a pillar protruding out of a surface of the substrate. The pillar includes a first doped region, a channel region and a second doped region from bottom to top. The gate is disposed on a sidewall at one side of the channel region. The base line is disposed on a sidewall at the other side of the channel region and not contacted with the gate. The gate dielectric layer is disposed between the gate and the channel region.

REFERENCES:
patent: 6806140 (2004-10-01), Kim et al.
patent: 7199419 (2007-04-01), Haller
patent: 2008/0099815 (2008-05-01), Sun

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