Vertical transistor and array with vertical transistors

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S330000, C257S331000, C257SE27060, C257SE27084, C257SE27085, C257SE27096, C257SE29262

Reexamination Certificate

active

07968937

ABSTRACT:
A vertical transistor includes a substrate, a semiconductor structure, a gate, a gate dielectric layer, and a conductive layer. The semiconductor structure is disposed on the substrate and includes two vertical plates and a bottom plate. The bottom plate has an upper surface connected to bottoms of the two vertical plates and a bottom surface connected to the substrate. The gate surrounds the semiconductor structure to fill between the two vertical plates, and the gate is disposed around the two vertical plates. The gate dielectric layer is sandwiched in between the gate and the semiconductor structure, and the conductive layer is disposed on the semiconductor structure and electrically connected with tops of the two vertical plates.

REFERENCES:
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patent: 5432739 (1995-07-01), Pein
patent: 6013548 (2000-01-01), Burns et al.
patent: 6077745 (2000-06-01), Burns, Jr. et al.
patent: 7015525 (2006-03-01), Forbes et al.
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patent: 2005/0032313 (2005-02-01), Forbes
patent: 2006/0097304 (2006-05-01), Yoon et al.
patent: 2006/0226463 (2006-10-01), Forbes
patent: 2007/0228437 (2007-10-01), Forbes
patent: 2008/0248620 (2008-10-01), Liu et al.

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