Vertical thin film transistor

Details Vertical thin film transistor Vertical thin film transistor

1997-01-06

1997-09-16

Tran, Minh-Loan

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257329, 257347, 257900, 257903, H01L 2976

Patent

active

056683910

ABSTRACT:
A thin film transistor includes a first insulating layer and a first conductive layer formed on a semiconductor substrate, a second insulating layer, a second conductive layer and a third insulating layer sequentially formed on the first conductive layer, a contact hole formed in the second insulating layer, second conductive layer and third insulating layer, a gate insulating layer formed along the sidewall of the contact hole, and a third conductive layer formed on the contact hole formed with the gate insulating layer thereon and surface of the third insulating layer to be used as a channel region and a source region by implanting an impurity, in which a drain region, a gate electrode and the source region are stacked, or vertically aligned on the substrate to allow a cell to occupy a small area for accomplishing high packing density of the cell and permit the gate electrode to encircle the channel region for improving a characteristic of the transistor, thereby stabilizing the cell.

REFERENCES:
patent: 5414289 (1995-05-01), Fitch et al.
"A Polysilicon Transistor Technology for Large Capacity SRAMs", Ikeda et al., 1990 IEEE International Electron Devices Meeting, Dec. 1990, pp. 469 to 472.
IEDM 92--pp. 823-826, Lili et al., "High Reliability and High Performance . . . LDD Structures", 1992.

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