Vertical synchronizing circuit

Details Vertical synchronizing circuit Vertical synchronizing circuit

1976-06-09

1977-05-24

Martin, John C.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

H04N 504

Patent

active

040259528

ABSTRACT:
A vertical synchronizing circuit wherein noise pulses or signals which may accompany vertical synchronizing pulses are locked out for a predetermined time subsequent to the receipt of a vertical synchronizing pulse is shown. A counter counts pulses at the horizontal or line deflection rate. At a particular count of the counter the vertical synchronizing circuit is conditioned for receipt of a vertical synchronizing pulse. Subsequent to the receipt of a vertical synchronizing pulse, the vertical synchronizing circuit is conditioned to be unresponsive to any received pulses until the counter again counts to the predetermined count.

REFERENCES:
patent: 3526714 (1970-09-01), Fisk et al.
patent: 3708621 (1973-01-01), Yamamoto
patent: 3751588 (1973-08-01), Eckenbrecht et al.

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