Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2001-03-27
2002-09-24
Wille, Douglas A. (Department: 2814)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C257S727000
Reexamination Certificate
active
06455351
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to vertically mountable semiconductor device packages. More specifically, the present invention relates to minimally packaged semiconductor devices which are vertically attached to a carrier substrate. Preferably, the present invention also relates to user-upgradable surface mount packages.
2. Background of Related Art
Vertical surface mount packages are known in the art. When compared with traditional, horizontally mountable semiconductor device packages and horizontally oriented multi-chip packages, many vertical surface mount packages consume less area on a circuit board or other carrier substrate than a horizontally mounted package of the same size. Many vertical surface mount packages may also have a superior ability to transfer heat than conventional horizontally mountable semiconductor device packages and horizontally oriented multi-chip packages. Thus, the semiconductor industry is finding that vertical surface mount packages offer advantages over their traditional, horizontally mountable counterparts. Various vertical surface mount packages are disclosed in U.S. Pat. No. Re. 34,794 (the “'794 patent”), issued to Warren M. Farnworth on Nov. 22, 1994; U.S. Pat. No. 5,444,304 (the “'304 patent”), issued to Kouija Hara and Jun Tanabe on Aug. 22, 1995; U.S. Pat. No. 5,450,289, issued to Yooung D. Kweon and Min C. An on Sep. 12, 1995; U.S. Pat. No. 5,451,815, issued to Norio Taniguchi et al. on Sep. 19, 1995; U.S. Pat. No. 5,592,019, issued to Tetsuya Ueda et al. on Jan. 7, 1997; and U.S. Pat. No. 5,635,760, issued to Toru Ishikawa on Jun. 3, 1997.
Some designs of vertical surface mount packages include wire bonded leads to operatively connect a semiconductor device to a circuit board which tend to increase the inductance and decrease the overall speed with which the device conducts electrical signals. The use of permanent wire bonds is necessary to electrically connect many such semiconductor devices to the circuit boards while the semiconductor devices are typically adhesively attached to the circuit board to be supported thereon, thereby preventing the vertical surface mount package from being readily user-upgradable.
Electrical connections may also be made between many types of electronic devices and a circuit board by means of sockets. For example, sockets are commonly employed to establish and maintain an electrical connection between a mother board and a daughter board, such as a single in-line memory module (SIMM). Exemplary devices are found in the following U.S. Pat. No. 4,781,612, issued to Roger L. Thrush on Nov. 1, 1998; U.S. Pat. No. 4,995,825, issued to Iosif Korsunsky et al. on Feb. 26, 1991; U.S. Pat. No. 5,209,675, issued to Iosif Korsunsky on May 11, 1993; U.S. Pat. No. 5,244,403, issued to Gregory J. Smith et al. on Sep. 14, 1993; and U.S. Pat. No. 5,256,078, issued to Nai H. Lwee and David J. Dutkowsky on Oct. 26, 1993. Each of the foregoing patents discloses the use of contacts within the socket which resiliently engage contacts on the daughter board to establish an electrical connection between the daughter board and the mother board.
However, none of those devices disclose the use of a socket for removably mounting a minimally packaged semiconductor device to a circuit board. The circuitry of a daughter board and the typical use of wire bonding to attach a semiconductor device thereto each tend to increase the inductance of such devices. Some socket-mountable daughter boards include more than one semiconductor device permanently attached thereto. Thus, such devices are not readily user-upgradable.
What is needed is a low impedance, vertically mountable semiconductor device package which has improved heat transferability and is readily user-upgradable.
SUMMARY OF THE INVENTION
The vertically mountable semiconductor device assembly of the present invention includes a semiconductor device, a retainer which engages the semiconductor device and a mounting element. The vertically mountable semiconductor device assembly of the present invention also includes an alignment device. The alignment device facilitates attachment of bond pads on the semiconductor device to their corresponding terminals on a carrier substrate.
The alignment device may include contacts to electrically connect a bond pad on the semiconductor device to a corresponding terminal on a carrier substrate. Alternatively, the bond pads may directly contact their corresponding terminals on a carrier substrate. Thus, as the mounting element is attached to the alignment device, an electrical connection is established between the semiconductor device and the carrier substrate.
The mounting element may include two downwardly extending clips, which flex outward during installation of the package onto the alignment device. The clips spring back to their relaxed position as they engage recessed areas of the alignment device. Removal of the vertically mountable semiconductor device package from the alignment device requires a slight outward flexion of the clips, such that they release the alignment device and may be moved upward relative thereto.
The present invention also includes a method of manufacturing the vertically mountable semiconductor device assembly and methods of designing and fabricating a semiconductor device that is useful in the vertically mountable semiconductor device assembly of the present invention. A computer which includes the vertically mountable semiconductor device package and assembly is also within the scope of the present invention.
Advantages of the present invention will become apparent to those of ordinary skill in the relevant art through a consideration of the appended drawings and the ensuing description.
REFERENCES:
patent: 4582386 (1986-04-01), Martens
patent: 4781612 (1988-11-01), Thrush
patent: 4995825 (1991-02-01), Korsunsky et al.
patent: 5209675 (1993-05-01), Korsunsky
patent: 5244403 (1993-09-01), Smith et al.
patent: 5256078 (1993-10-01), Lwee et al.
patent: 5266833 (1993-11-01), Capps
patent: RE34794 (1994-11-01), Farnworth
patent: 5444304 (1995-08-01), Hara et al.
patent: 5449297 (1995-09-01), Bellomo et al.
patent: 5450289 (1995-09-01), Kweon et al.
patent: 5451815 (1995-09-01), Taniguchi et al.
patent: 5592019 (1997-01-01), Ueda et al.
patent: 5635760 (1997-06-01), Ishikawa
patent: 5668409 (1997-09-01), Gaul
patent: 5821615 (1998-10-01), Lee
patent: 6010920 (2000-01-01), Hellgren et al.
Brooks Jerry M.
Farnworth Warren M.
Kinsman Larry D.
Lee Terry R.
Moden Walter L.
TraskBritt
Wille Douglas A.
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