Vertical sub-micron CMOS transistors on (110), (111), (311),...

Details Vertical sub-micron CMOS transistors on (110), (111), (311),... Vertical sub-micron CMOS transistors on (110), (111), (311),...

1999-08-13

2002-11-19

Jackson, Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Physical configuration of semiconductor

With specified crystal plane or axis

C257S351000, C257S365000, C257S368000, C257S369000, C257S627000, C257S628000

Reexamination Certificate

active

06483171

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of improving hole mobility and thus velocity saturating vertical transistors by forming the vertical transistors on crystal surfaces of higher order. Also, the present invention deals with the method of forming the vertical transistors and their use in memory cells.
2. Description of the Related Art
The nearly universal standard silicon wafer crystal orientation for VLSI (“Very Large Scale Integration”) is the (100) orientation. This orientation was chosen over the previously used (111) orientation due to its low surface state density on thermally oxidized surfaces, 9×10
10
/cm
2
versus 5×10
11
/cm
2
as shown in FIG.
1
C.
FIGS. 1A and 1B
simply illustrate conventional crystal orientations.
The difference between high and low surface state densities was originally a particularly important consideration for NMOS technology in that a high surface state density makes it difficult to control active and parasitic device threshold voltages as compared to low surface state densities. For the (110) surface orientation, the surface state charge density is 2×10
11
e/cm
2
, which is about double that of the (110) orientation. In present day technology, however, this would amount to less than 0.10 V offset in active device threshold voltage and is readily compensated by the surface threshold voltage ion implant, body bias, and/or potentials of the backgates in SOI (“silicon-on-insulator”) technology.
Even in the case of (111) surfaces, a very pessimistic estimate of the surface charge density of 5×10
11
/cm
2
would result in a threshold voltage shift of only 0.25 V in present day technology. The original benefit to NMOS device was that the electron mobility in inversion layers is greater on the (110) surface than on other low order planes. However, it was pointed out in U.S. Pat. No. 4,857,986 to Kinugawa that for modern day CMOS technology with sub-micron devices, a different set of tradeoffs exist. In such short channel devices, the NFETS operate largely in velocity saturation resulting in a source to drain current that is independent of orientation. The PFETs, on the other hand, are less likely to be in velocity saturation and thus would benefit from optimizing the choice of crystal orientation around the inversion layer hole mobility.
Since the inversion layer hole mobility can be twice as high on the (110) surfaces than on the (110) surfaces, as is shown in
FIG. 1C
, which illustrates assorted properties of the various crystal orientations, overall circuit performance will be enhanced by basing the sub-micron CMOS technology on (110) oriented substrate wafers.
Both U.S. Pat. No. 4,857,986 to Kinugawa and U.S. Pat. No. 4,768,076 to Aoki et al. disclose planar bulk and SOI technologies that either use the (110) crystal wafer orientation or a recrystallized (110) surface layer. However, significant advantages have been obtained by using not just the (110) surface, which are not commonly available, but also (110), (111) and higher order surfaces on (110) and (111) orientation wafers, which are commonly available.
FIG. 2
is a graph showing 70% to 80% higher hole mobility for conduction in the <100> directions on (110) surfaces and for conduction on (111) surfaces than on (100) surfaces.
Moreover, traditional thin film transistors as shown in
FIG. 6A
have an outward crystallization structure, which causes the current to flow across grain boundaries. This traditional horizontal transistor thus has a tendency to have low carrier mobilities.
Thus, the present invention seeks to achieve more uniform current flow as well as improve surface area utilization of the crystal surface.
SUMMARY OF THE INVENTION
The present invention seeks to mitigate the problems of the prior art by forming vertical transistors on higher order crystal orientations. The thus-formed vertical transistors have side gates, and may have back side gates, rather than a gate formed on top of the transistor, i.e. on the opposite side of the transistor from the substrate. The side gates and the back side gates facilitate current flow in the transistor.
The basic premise of the present invention is to increase the hole mobility in the transistors by forming the transistors on surfaces with higher order crystal orientations. By higher order, we mean surfaces which include the (110), (111), (311), and (511) surfaces as well as higher order surfaces. Such an increase in the hole mobility makes it more likely that the transistors, both NMOS and PMOS, are velocity saturated, thus making the transistors function better. Furthermore, the thus formed transistors are biased to operate in veolcity saturation. Moreover, this improvement in hole mobility is a direct result of forming the transistors on higher order crystal orientations.
The operation of the transistor is further enhanced by forming the transistors vertically, rather than horizontally. The vertical transistors allow for a shorter channel length, thus improving transistor operation. The thus formed transistors may be utilized in digital logic circuits, for example, in memory cells, such as DRAMs or SRAMs, among others.


REFERENCES:
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patent: 4768076 (1988-08-01), Aoki et al.
patent: 4857986 (1989-08-01), Kinigawa
patent: 5616935 (1997-04-01), Koyama et al.
patent: 5895948 (1999-04-01), Mori et al.
patent: 5942768 (1999-08-01), Zhang
patent: 5963800 (1999-10-01), Augusto
patent: 5991225 (1999-11-01), Forbes et al.
patent: 6037610 (2000-03-01), Zhang et al.
patent: 6307214 (2001-10-01), Ohtani et al.
Balk; “Orientation Dependence of Built-In Surface Charge on Thermally Oxidized Silicon”; Proceedings of the IEEE, vol. 53, p. 2133-34, 1965.
Carr et al.; “MOS/LSI Design and Applications”; McGraw-Hill Book Company, p. 37, 49-52, 1972.
Sato et al.; “Drift-Velocity Saturation of Holes in Si Inversion Layers”; J. Phys. Soc. Japan, vol. 31, p. 1346, 1971.
Sato et al.; “Mobility Anistropy of Electrons in Inversion Layers on Oxidized Silicon Surfaces”; Physical Review B, vol. 4, No. 6, Sep. 15, 1971; p. 1950-60.
Vitkavage et al.; “An investigation of Si-SiO2 interface charges in thermally oxidized (100), (110), (111), and (511) silicon”; J. Appl. Phys. vol. 68, No. 10, Nov. 15, 1990; p. 5262-72.

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