Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-05-31
2003-04-15
Fahmy, Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S323000, C438S259000
Reexamination Certificate
active
06548856
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the manufacture of semiconductor memory devices and more particularly to a method of manufacture of vertical FET devices formed in trenches in a semiconductor substrate and the devices formed thereby.
2. Description of Related Art
Some background information is as follows:
1. It is necessary to employ process steps which are different from conventional processes to scale down for deep sub-micron devices.
2. There is an issue of compatibility in embedded flash memory devices.
3. There has been low drain current in the past.
U.S. Pat. No. 5,108,938 of Solomon for “Method of Making a Trench Gate Complimentary Metal Oxide Semiconductor Transistor” shows a FET (Field Effect Transistor) with the source (S) and drain (D) regions on the substrate surface separated by a trench.
U.S. Pat. No. 5,391,506 of Tada et al. for “Manufacturing Method for Semiconductor Devices with Source/Drain Formed in Substrate Projection” shows a method for manufacturing semiconductor devices with source/drain regions formed in a substrate projection. A projection is formed in a substrate by anisotropic etching and a transistor is contained in the projection. The central portion of the projection covered with a gate electrode is formed as a channel region, and drain/source regions are formed on both sides of the projection by oblique ion implantation with the gate electrode as a mask.
U.S. Pat. No. 5,312,767 of Shimizu et al, for “MOS Type Field Effect Transistor and Manufacturing Method Thereof” shows a vertical SOI (Silicon On Insulator) transistor that has the S and D regions on opposite ends of a trench. However the device is not a Flash memory device.
U.S. Pat. No. 5,229,310 of Sivan “Method of Making a Self-Aligned Vertical Thin-Film Transistor in a Semiconductor Device” shows an EEPROM with a vertical orientation in a trench.
See Woo et al. U.S. Pat. No. 5,210,047 for “Process for Fabricating a Flash EPROM Having Reduced Cell Size”.
SUMMARY OF THE INVENTION
Objects of this invention are as follows:
1. Use vertical channel and drain/source structure to reduce cell area substantially.
2. Use trench floating polysilicon method to planarize front gate topography in a way which is fully compatible with logic manufacturing process.
3. Increase drain current by providing a large conductive width of the structure.
Features of the present invention are as follows:
1. An area scale down is more possible than in the past.
2. Gate patterning and planarization are very compatible with the logic circuit manufacturing process.
3. High drain current is available during programming and reading.
In accordance with this invention a method is provided for forming a vertical transistor memory device by a process with the following steps. Before forming the trenches, FOX regions are formed between the rows. Then form a set of trenches with sidewalls and a bottom in a semiconductor substrate with threshold implant regions the sidewalls. Form doped drain regions near the surface of the substrate and doped source regions in the base of the device below the trenches with oppositely doped channel regions therebetween. Form a tunnel oxide layer over the substrate including the trenches. Form a blanket thin floating gate layer of doped polysilicon over the tunnel oxide layer extending above the trenches. Etch the floating gate layer leaving upright floating gate strips of the floating gate layer along the sidewalls of the trenches. Form an interelectrode dielectric layer composed of ONO over the floating gate layer and over the tunnel oxide layer. Form a blanket thin control gate layer of doped polysilicon over the interelectrode dielectric layer. Pattern the control gate layer into control gate electrodes. Form spacers adjacent to the sidewalls of the control gate electrode.
Preferably, an array of FET cells is formed in rows and columns, with the rows being orthogonally arranged with respect to the columns with the cells in a single row having a common source region and the cells in columns having separate source regions. Prior to forming the threshold implant regions formed within the trench sidewalls, a source connect implant is formed in the bottoms of the trenches. Before forming the trenches, FOX regions are formed between the rows.
In accordance with this invention, a vertical stack gate flash memory device is provided made in accordance with the above method.
REFERENCES:
patent: 5108938 (1992-04-01), Solomon
patent: 5210047 (1993-05-01), Woo et al.
patent: 5229310 (1993-07-01), Sivan
patent: 5312767 (1994-05-01), Shimizu et al.
patent: 5391506 (1995-02-01), Tada et al.
patent: 5460988 (1995-10-01), Hong
patent: 5460989 (1995-10-01), Wake
patent: 5506431 (1996-04-01), Thamos
patent: 5705415 (1998-01-01), Orlowski et al.
patent: 5945705 (1999-08-01), Liu et al.
Chen Shui-Hung
Liang Mong-Song
Lin Chrong-Jung
Ackerman Stephen B.
Fahmy Wael
Jones II Graham S.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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