Vertical stack type multi-chip package having improved...

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings

Reexamination Certificate

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Details

C257S790000, C257S706000, C257S777000, C257S723000, C257S796000, C257SE23126, C257SE23116, C257SE23134

Reexamination Certificate

active

07868443

ABSTRACT:
A vertical stack type multi-chip package is provided having improved reliability by increasing the grounding performance and preventing the decrease in reliability of the multi-chip package from moisture penetration into a lower semiconductor chip. The vertical stack type multi-chip package comprises an organic substrate having a printed circuit pattern on which a semiconductor chip is mounted. A first semiconductor chip is mounted on a die bonding region of the organic substrate and is electrically connected to the organic substrate through a first wire. A metal stiffener is formed on the first semiconductor chip and connected to the organic substrate by a first ground unit around the first semiconductor chip. An encapsulant is used to seal the first semiconductor chip below the metal stiffener. A second semiconductor chip, which is larger in size than that the first semiconductor chip, is mounted on the metal stiffener and connected by a second ground unit. The second semiconductor chip is connected to the organic substrate by a second wire. A mold resin seals the second semiconductor chip and a solder ball is bonded to a solder ball pad below the organic substrate.

REFERENCES:
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patent: 6618267 (2003-09-01), Dalal et al.
patent: 6737750 (2004-05-01), Hoffman et al.
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patent: 7049691 (2006-05-01), Karnezos
patent: 2004/0051170 (2004-03-01), Kawakami et al.
patent: 2004/0183180 (2004-09-01), Chung et al.
patent: 2004/0231872 (2004-11-01), Arnold et al.

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