Vertical spacer forming and related transistor

Details Vertical spacer forming and related transistor Vertical spacer forming and related transistor

2011-08-09

2011-08-09

Garber, Charles D (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

Reexamination Certificate

active

07993989

ABSTRACT:
Methods include, for example, forming a vertically disposed active region on a substrate; forming a first gate over a portion of the vertically disposed active region; forming a dielectric over the portion; exposing an upper surface of the first gate; forming a second gate over the upper surface; and forming a spacer pocket region between the vertically disposed active region, the first gate and the dielectric, wherein the spacer pocket region is self-aligned to a lower surface of the second gate and has a substantially uniform thickness from an upper to a lower extent thereof.

REFERENCES:
patent: 2002/0028541 (2002-03-01), Lee et al.
patent: 2005/0201155 (2005-09-01), Shih
patent: 2005/0263795 (2005-12-01), Choi et al.
patent: 2006/0154423 (2006-07-01), Fried et al.
patent: 2009/0224339 (2009-09-01), Gogoi et al.

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