Vertical semiconductor device having alternating...

Details Vertical semiconductor device having alternating... Vertical semiconductor device having alternating...

2001-12-31

2004-03-02

Zarabian, Amir (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

With means to increase breakdown voltage threshold

Field relief electrode

C257S302000, C257S328000, C257S329000, C257S339000, C438S259000, C438S246000, C438S270000

Reexamination Certificate

active

06700175

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a high voltage semiconductor device. More particularly, the present invention relates to a vertical semiconductor device and a method of manufacturing the same.
BACKGROUND OF ART
FIG. 34
is a cross-sectional view showing a high voltage MOSFET disclosed in U.S. Pat. No. 5,216,275. The structure of this high voltage MOSFET
300
is described below. The high voltage MOSFET
300
is a vertical MOSFET. The high voltage MOSFET
300
is formed on a semiconductor substrate. The semiconductor substrate includes an n
+
-type drain region
304
. p-type semiconductor regions
302
and n-type semiconductor regions
301
are formed on the drain region
304
, arranged alternately p
+
-type semiconductor regions
303
are formed on the p-type semiconductor regions
302
. The end sections of the p
+
-type semiconductor regions
303
are located on the n-type semiconductor regions
301
. A gate electrode
309
is formed on the n-type semiconductor region
301
and the sidewalls of the p
+
-type semiconductor regions
303
through a gate insulating film
308
. A pair of n
+
-type source regions
305
is formed on the surfaces of the p
+
-type semiconductor regions
303
with an interval therebetween. Source electrodes
310
are formed on the p
+
-type semiconductor regions
303
between the n
+
-type source regions
305
.
The operation of the high voltage MOSFET
300
is described below. The operation in the case where the high voltage MOSFET
300
is in an ON state is described first. When a positive voltage is applied to the gate electrode
309
, channel regions are formed in the p
+
-type semiconductor regions
303
in regions facing the gate insulating film
308
. Electrons are supplied from the source regions
305
and reach the drain region
304
through the channel regions and the n-type semiconductor region
301
. In this case, the ON voltage of the high voltage MOSFET
300
is mainly determined by a voltage drop by the resistance of the n-type semiconductor region
301
.
The operation in the case where the high voltage MOSFET
300
is in an OFF state is described below. Either 0 V or a negative voltage is applied to the gate electrode
309
. This causes the channel regions to disappear. In the case where the drain voltage is about 10 V, depletion layer is formed and spread along junctions formed between the n-type semiconductor region (drain region
304
and n-type semiconductor region
301
make up the n-type semiconductor region) and the p-type semiconductor regions (p-type semiconductor regions
302
and p
+
-type semiconductor regions
303
make up the p-type semiconductor regions). The widths of the n-type semiconductor region
301
and the p-type semiconductor region
302
are small. Therefore, the n-type semiconductor region
301
and the p-type semiconductor regions
302
are depleted completely as the drain voltage increases. Specifically, the breakdown voltage is sustained by the structural section in which the n-type semiconductor regions
301
and the p-type semiconductor regions
302
are arranged alternately.
The above U.S. Patent describes the high voltage MOSFET having the structural section in which the n-type semiconductor regions
301
and the p-type semiconductor regions
302
are arranged alternately as a device with a high breakdown voltage and a low ON voltage.
The method of forming the p-type semiconductor regions
302
and the n-type semiconductor regions
301
of the high voltage MOSFET
300
shown in
FIG. 34
is described below. An n-type (or p-type) epitaxial layer is epitaxially grown on the semiconductor substrate which becomes the drain region
304
. The n-type (or p-type) epitaxial layer is selectively removed, thereby forming trenches which reach the drain region
304
. The remaining n-type (or p-type) epitaxial layer becomes the n-type semiconductor regions
301
(or p-type semiconductor regions
302
). The trenches are filled with the p-type semiconductor regions
302
(or n-type semiconductor regions
301
) by epitaxial growth.
As described above, the structural section in which the p-type semiconductor regions
302
and the n-type semiconductor regions
301
are arranged alternately is fabricated by forming the trenches by selectively removing the semiconductor layer of first conductive type and filling the trenches with the semiconductor layers of second conductive type by epitaxial growth. The epitaxial growth step is generally a high temperature process. Therefore, in the case of fabricating the structural section in which the p-type semiconductor regions and the n-type semiconductor regions are arranged alternately using the above method, phenomena may occur in which impurities in the semiconductor layers of second conductive type are diffused into the semiconductor layers of first conductive type and impurities in the semiconductor layers of first conductive type are diffused into the semiconductor layers of second conductive type during the formation of the semiconductor layers of second conductive type. Therefore, it is difficult to miniaturize the structural section in which the p-type semiconductor regions and the n-type semiconductor regions are formed, arranged alternately.
DISCLOSURE OF INVENTION
The present invention has been attained to solve the above problems. An objective of the present invention is to provide a vertical semiconductor device including a structural section in which a first semiconductor region of first conductive type and a second semiconductor region of second conductive type are arranged alternately without filling trenches by epitaxial growth, and a method of manufacturing the same.
The present invention relates to a vertical semiconductor device including a structural section in which a first semiconductor region of first conductive type and a second semiconductor region of second conductive type are arranged alternately,
wherein a breakdown voltage is sustained by the structural section,
wherein a graded junction is formed between the first semiconductor region and the second semiconductor region, and
wherein an impurity profile of first conductive type in the graded junction is graded along a direction in which the first and second semiconductor regions are arranged alternately.
According to the vertical semiconductor device of the present invention, since the distribution of the impurities of first conductive type is graded in the first semiconductor region, depletion layer can be spread widely in a region in which the concentration of the impurities of first conductive type is lower. Therefore, the first semiconductor region and the second semiconductor region can be easily depleted even if the widths of these regions are comparatively greater, whereby an increase in the breakdown voltage can be realized.
The vertical semiconductor device including the above structural section has a high breakdown voltage and a low ON voltage. The reasons there for are described below taking a high voltage vertical MOS field effect transistor as an example. The breakdown voltage is an important parameter which determines the performance of the transistor. In the case where a section corresponding to the structural section formed of only the first semiconductor region of first conductive type, the breakdown voltage is determined by the junction breakdown voltage at the junction between the first semiconductor region and a second conductive type body region (channel is formed in body region). The junction breakdown voltage increases as the impurity concentration in the first semiconductor region decreases. This is because the length of the depletion layer increases as the impurity concentration decreases. The length of the depletion layer refers to the length of the depletion layer in a source-drain direction. However, the resistance of the first semiconductor region increases as the impurity concentration decreases. This causes the ON voltage of the transistor to be increased. In the transistor having such a structure, since th

Affiliated with

Also associated with

Rating

Vertical semiconductor device having alternating... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Vertical semiconductor device having alternating..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Vertical semiconductor device having alternating... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3261248