Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-01-15
2003-09-09
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S297000, C257S304000, C257S390000, C257S391000, C257S392000, C257S302000, C438S289000, C438S242000
Reexamination Certificate
active
06617633
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application Ser. No. 90132743, filed Dec. 28, 2001.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a semiconductor device and the fabrication thereof. More particularly, the present invention relates to a vertical read-only memory (ROM) and the fabrication thereof.
2. Description of Related Art
A conventional read-only memory stores 1-bit data in each memory cell and the size of the memory cell is restricted by the minimum linewidth of the lithography process. Therefore, it is not easy to scale down the conventional read-only memory. Besides, a conventional read-only memory is programmed by implanting a high concentration of ions with a conductivity type different from that of a source/drain into the channel regions of the selected memory cells, so as to raise the threshold voltage of the selected memory cells. However, the threshold voltage easily shifts to cause a leakage current because of a non-uniform dosage distribution of the ion implantation.
SUMMARY OF THE INVENTION
In view of the above-mentioned problems, the present invention provides a vertical read-only memory and a method for fabricating the same, by which a more uniform threshold voltage distribution can be obtained.
This invention also provides a vertical read-only memory and a method for fabricating the same, by which the leakage in a memory cell can be decreased.
The vertical read-only memory of this invention comprises a gate on a substrate, a source and a drain at the bottom of a trench in the substrate, a polysilicon bit-line in the trench, and a dielectric layer separating the polysilicon bit-line and the substrate of the side-wall of the trench. The polysilicon bit-line electrically connects with the source/drain. The substrate of the side-wall of the trench adjacent to the gate serves as a coding region.
Since there are two side-walls of the trench adjacent to the gate at the source side and at the drain side, respectively, the vertical read-only memory has two coding regions in one memory cell and thus can store two bits in one memory cell. Further, the two bits are stored in two coding regions perpendicular to the surface of the wafer, so that miniaturizing the memory device is not restricted by the minimum linewidth of the lithography process. Consequently, the memory device can be easily scaled down. In addition, the threshold voltage of the channel in the substrate of the side-wall of the trench is determined by the thickness of the dielectric layer, which can be well controlled by the conditions for forming the dielectric layer. Therefore, the threshold voltage (V
T
) distribution of the memory device is more uniform, so that the leakage current can be decreased.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5300804 (1994-04-01), Arai
patent: 5618742 (1997-04-01), Shone et al.
patent: 6265748 (2001-07-01), Hofmann et al.
Crane Sara
Im Junghwa
J.C. Patents
Macronix International Co. Ltd.
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