Vertical power MOSFET having reduced sensitivity to variations i

Details Vertical power MOSFET having reduced sensitivity to variations i Vertical power MOSFET having reduced sensitivity to variations i

1996-03-15

1998-09-29

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257332, 257341, 257401, 257549, 438 20, 438 40, 438228, H01L 2972

Patent

active

058148582

ABSTRACT:
A vertical power MOSFET, which could be a trench-gated or planar double-diffused device, includes an N+ substrate and an overlying N-epitaxial layer. An N-type buried layer is formed in the epitaxial layer and overlaps the substrate, the buried layer having a dopant concentration which is greater than the dopant concentration of the epitaxial layer but less than the dopant concentration of the substrate. The ion implant which is used to create the buried layer is preferably performed after most of the high temperature operations in the fabrication process in order to minimize the diffusion of the buried layer. This controls the distance between the top edge of the buried layer and the drain-body junction of the MOSFET and allows the breakdown voltage and on-resistance of the MOSFET to be determined substantially without regard to the thickness of the epitaxial layer.

REFERENCES:
patent: 5045900 (1991-09-01), Tamagawa
patent: 5282018 (1994-01-01), Hiraki et al.

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