Vertical power MOS device with increased ruggedness and method o

Details Vertical power MOS device with increased ruggedness and method o Vertical power MOS device with increased ruggedness and method o

1992-02-25

1993-12-07

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257339, 257341, H01L 2910

Patent

active

052685861

ABSTRACT:
A semiconductor device of improved ruggedness is provided which comprises a semiconductor substrate having a region of a first conductivity type on a major surface thereof; a first base region of opposite conductivity type formed selectively within said regions of first conductivity type; a second base region of opposite conductivity type formed selectively within said first base region and having a higher impurity concentration than that of said first base region; a source region of one conductivity type formed within said first and second base regions and overlying said second base region; and a polysilicon gate electrode opposed to a channel region with a gate insulating layer interposed therebetween; wherein the second base region and the source region are formed substantially entirely within the first base region; the second base region is smaller in depth than the first base region and is formed at a distance sufficiently close to the channel region to effectively reduce parasitic resistance in the first base region, the lateral edges of the second base region being substantially aligned with the lateral edges of the gate electrode; the first base region and the source region are formed by sequential implantation through the polysilicon gate electrode region using the polysilicon gate electrode as a self-aligned mask, followed by implantation of the second base region without substantial lateral diffusion using the polysilicon gate electrode as a mask; and the polysilicon gate electrode is of a thickness sufficient to mask for selected depths of implantation in the first base region.

REFERENCES:
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patent: 4680604 (1987-07-01), Nakagawa et al.
patent: 4774198 (1988-09-01), Contiero et al.
patent: 4809047 (1989-02-01), Temple
Chang et al, "Insulated Gate Bipolar Transistor (IGBT) with a Trench Gate Structure", IEDM 1987, pp. 674-677.
Temple et al. "MCT (MOS Controlled Thyristor) Reliability Investigation", IEDM 1988, pp. 618-621.
SIPMOS Process, Siemens Component Data Book, 1987/1988.
Dr. M. J. Humphreys, Philips Components, Hazel Grove, Stockport, Cheshire, U.K., "The Avalanche Ruggedness of Power MOSFETS", Electronique de Puissance, No. 38, pp. 18-25, Apr., 1990.
Love et al, IEEE Trans. Elect. Dev., ED-31,817 (1984).

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