Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-08-27
2004-04-06
Booth, Richard A. (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S321000, C438S259000
Reexamination Certificate
active
06717205
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The present invention relates to a vertical non-volatile semiconductor memory cell and an associated manufacturing method, and in particular to an EPROM (Erasable Programmable Read Only Memory), an EEPROM (Electronically Erasable Programmable Read Only Memory) and a FLASH-EEPROM memory cell with low area requirements.
Rewritable non-volatile semiconductor memory cells are increasingly gaining importance in highly integrated circuits because they can store variable data over a long period in, for example, chip cards, multimedia cards and what are referred to as smart cards, without the use of a voltage supply. The various applications result in different requirement profiles which require different technological implementations. What are referred to as embedded non-volatile memories in which the non-volatile storage function is implemented simultaneously with further functions while taking into account their requirement profiles on the same chip are becoming increasingly important.
Depending on the type of non-volatile semiconductor memory cells used, in particular depending on the programming and erasure methods on which they are based, a fundamental distinction is made between EPROMs, EEPROMs and FLASH-EEPROM memories. Suitable memories, which can be embedded are almost exclusively electrically programmable and erasable as well as repeatedly re-writable memories (EEPROM, FLASH).
For these applications, known, conventional non-volatile semiconductor cells are usually composed of a semiconductor substrate, an isolating tunnel oxide layer, a floating gate layer or charge storage layer, an isolating dielectric layer and a conductive control layer which are formed on the surface of the semiconductor substrate. In order to store information, charges are introduced via the tunnel oxide layer into the floating gate layer from a channel region formed in the semiconductor substrate. Methods for introducing the charges into the floating gate layer are, for example, the injection of hot charge carriers and Fowler-Nordheim tunneling.
However, a disadvantage with such conventional non-volatile semiconductor memory cells is, on the one hand, the relatively high amount of space required, which is a result in particular of their formation on the surface of the semiconductor substrate. On the other hand, the space required cannot be reduced by scaling or shrinking as is known with logic technologies because the minimum structure sizes are largely fixed as a result of the programming and erasure voltages which are necessary due to the physical mechanism.
Therefore, three-dimensional arrangements for non-volatile semiconductor memory cells are increasingly being proposed in order to reduce the area further, in which arrangements, for example, the isolating tunnel oxide layer, the floating gate layer and the control layer are arranged vertically in the semiconductor substrate.
FIG. 1
shows a sectional view of such a vertical non-volatile semiconductor memory cell as is known, for example, from International Publication WO97/02599. According to this publication, a trench
140
is formed in a semiconductor substrate
200
which has, for example, a weakly doped p type region
100
, a p type doped well
110
and a highly doped n
+
type region
120
. By means of an ancillary layer
130
and a mask layer (not illustrated), a further highly doped n
+
type region
150
is formed on the bottom of the trench
140
. The highly doped n
+
type regions
150
and
120
constitute here what are referred to as drain and source regions of the vertical non-volatile semiconductor memory cell. A tunnel oxide layer
160
serving as a dielectric layer is formed on the walls and on the bottom of the trench
140
. Adjoining this are the floating gate layer
170
for storing charges and a second dielectric layer
180
which is composed of an ONO (Oxide-Nitride-Oxide) layer sequence. In order to drive the non-volatile semiconductor memory cell, there is a control layer
190
, which is composed of highly doped polysilicon, and which is located on the second dielectric layer
180
.
In this way, a vertical non-volatile semiconductor memory cell requiring a smaller area is obtained because the minimum necessary channel length of the storage cell now extends vertically in the semiconductor substrate
200
, and a greater degree of reduction of the structure sizes on the surface of the semiconductor substrate is made possible. However, a disadvantage with such a conventional vertical non-volatile semiconductor memory cell is the low data retention properties which result, in particular, from a charge loss in the direction of the semiconductor substrate
200
.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a vertical non-volatile semiconductor memory cell and an associated manufacturing method which overcomes the above-mentioned disadvantageous of the prior art apparatus and methods of this general type. In particular, it is an object of the invention to provide a vertical non-volatile semiconductor memory cell and an associated manufacturing method in which improved data retention properties or an improved “retention time” are/is obtained.
With the foregoing and other objects in view there is provided, in accordance with the invention, a vertical non-volatile semiconductor memory cell that includes a substrate having a surface, a drain region, a channel region and a source region. A trench is formed in the substrate from the source region to the drain region. The trench is formed vertically, essentially perpendicular to the surface of the substrate. The trench has trench walls. A first dielectric layer is formed essentially on the trench walls. A charge storage layer for storing charges is essentially formed on the first dielectric layer. The charge storage layer has a surface. A second dielectric layer is formed at least partially on the surface of the charge storage layer. A control layer is formed essentially on the surface of the second dielectric layer and that has a surface. A trench extension is formed essentially underneath the trench. The trench extension has a surface. A third dielectric layer is located on the surface of the trench. A filler material is provided for at least partially filling the trench extension.
Greatly improved data retention properties are obtained in a particularly cost-effective way, in particular by using a trench extension which is formed essentially underneath a trench in which the vertical non-volatile semiconductor memory cell is located, because a charge loss from a charge-storing layer into a substrate is greatly reduced. The trench extension here has a third dielectric layer on its trench surface and is at least partially filled with an isolating or electrically conductive filler material.
A further improvement in the data retention properties is obtained in the case of an electrically conductive filler material by means of an additional isolation of the charge storage layer of the semiconductor memory cell from the filler material of the trench extension. The “retention time” can thus be further improved.
However, this additional isolation between the filler material and the charge storage layer can also be dispensed with as an alternative, or in order to reduce the costs, in which case very good data retention properties for the non-volatile semiconductor memory cell can continue to be obtained if the third dielectric layer on the surface of the trench extension is suitably configured.
In order to optimize a coupling factor, a second dielectric layer and a control layer can extend to the substrate, both within the trench and within the trench extension, as a result of which minimum programming voltages can be set as a function of a respective layout and associated parasitic capacitances.
A first dielectric layer is preferably composed of a tunnel layer, and a second and third dielectric layer are preferably composed of an ONO layer sequence. The vertical non-volatile semiconductor me
Booth Richard A.
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Stemer Werner H.
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