Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – Combined with field effect transistor
Reexamination Certificate
2003-03-13
2004-12-21
Everhart, Caridad (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Regenerative type switching device
Combined with field effect transistor
C257S302000, C257S256000, C257S261000, C257S288000, C257S798000, C438S268000
Reexamination Certificate
active
06833567
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a vertical nano-sized transistor and a method for manufacturing the same. More specifically, the present invention relates to a vertical nano-sized transistor using carbon nanotubes capable of achieving high-density, or tera-bit scale, integration and a method for manufacturing the same.
2. Description of the Related Art
A switching device fabricated using a conventional silicon substrate is generally constructed such that an impurity diffusion region, an isolation region and a channel region are horizontally connected on the silicon substrate. An integrated circuit consisting of multiple switching devices is constructed such that the individual switching devices are horizontally arranged to be highly integrated. A problem arising from forming an impurity diffusion region and an isolation region on a silicon substrate is that there are limits in processing precision and integration. A result of the limitations imposed by forming an impurity diffusion region and an isolation region on a silicon substrate is the difficulty to decrease the size of the switching device.
A metal oxide semiconductor field effect transistor (MOSFET) is one of the most typically used fine switching devices. The area of a 256 Mega DRAM having a minimum pattern size of 0.25 &mgr;m is approximately 0.72 &mgr;m
2
; the area of a 1 Giga DRAM having a minimum pattern size of 0.18 &mgr;m is approximately 0.32 &mgr;m
2
; the area of a 4 Giga DRAM having a minimum pattern size of 0.13 &mgr;m is approximately 0.18 &mgr;m
2
, and the area of a 16 Giga DRAM having a minimum pattern size of 0.1 &mgr;m is approximately 0.1 &mgr;m
2
.
In order to overcome problems in miniaturizing conventional switching devices, a switching device using carbon nanotubes has been proposed. However, the proposed device still has a horizontal structure similar to that of other conventional switching devices making it quite difficult to control the individual carbon nanotubes.
As a result, it is difficult to achieve high-density integration of switching devices using carbon nanotubes.
SUMMARY OF THE INVENTION
In order to solve the aforementioned problems, it is a feature of an embodiment of the present invention to provide by vertical growth and selective deposition a vertical transistor ranging in size from several tens of nanometers to one micron using tera-bit scale carbon nanotubes as channels where each of the carbon nanotubes has a diameter of several nanometers and is grown on a nonconductive substrate having nano-sized holes. The lower and upper parts of each carbon nanotube are connected to a source and a drain, respectively, with a gate interposed between the source and the drain for performing switching.
It is another feature of an embodiment of the present invention to provide a method of manufacturing the vertical nano-sized transistor.
In order to provide for these and other features of the present invention, there is provided a vertical nano-sized transistor using carbon nanotubes including an insulating layer preferably formed of one material selected from Al
2
O
3
and Si, the insulating layer having holes with nano-sized diameters; carbon nanotubes vertically aligned in the holes; gates formed over the insulating layer in the vicinity of the carbon nanotubes; a nonconductor film deposited on the gates to fill the holes; drains formed over the nonconductor film and the carbon nanotubes; and sources formed under the insulating layer and the carbon nanotubes. The sources and the drains are preferably formed of metal films.
According to another feature of an embodiment of the present invention, there is provided a method of manufacturing a vertical nano-sized transistor using carbon nanotubes by forming sources on a semiconductor substrate; forming an insulating layer using a nonconductor material, and the nonconductor material being preferably Al
2
O
3
or Si; forming holes in portions of the insulating layer corresponding to the sources, the holes having nano-sized diameters and being spaced at intervals of several nanometers; vertically growing carbon nanotubes on the sources in the holes achieved preferably by one method selected from chemical vapor deposition (CVD), electrophoresis and mechanical compression; forming gates in the vicinity of the carbon nanotubes; depositing a nonconductor film over the gates to fill the holes; and forming drains over the nonconductor film and the carbon nanotubes.
Another feature of an embodiment of the present invention provides a vertical nano-sized transistor using carbon nanotubes including an insulating layer formed preferably of either Al
2
O
3
or Si, and the insulating layer having holes with nano-sized diameters; carbon nanotubes vertically aligned in the holes; drains formed over the insulating layer and the carbon nanotubes; a nonconductor film deposited on the drains; gates formed over the nonconductor film; and sources formed under the insulating layer and the carbon nanotubes. The sources and the drains are preferably formed of metal films.
Still another feature of an embodiment of the present invention provides a method of manufacturing a vertical nano-sized transistor using carbon nanotubes by forming sources on a semiconductor substrate; forming an insulating layer using a nonconductor material preferably of either Al
2
O
3
or Si; forming holes in portions of the insulating layer corresponding to the sources, the holes having nano-sized diameters and being spaced at intervals of several nanometers; vertically growing carbon nanotubes on the sources in the holes, achieved preferably by one method selected from chemical vapor deposition (CVD), electrophoresis and mechanical compression; forming drains over the nonconductor film and the carbon nanotubes; depositing a nonconductor film over the drains; and forming gates over the nonconductor film.
These and other features of the present invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description that follows.
REFERENCES:
patent: 6034389 (2000-03-01), Burns et al.
patent: 6038060 (2000-03-01), Crowley
patent: 6297063 (2001-10-01), Brown et al.
patent: 6340822 (2002-01-01), Brown et al.
patent: 6359288 (2002-03-01), Ying et al.
patent: 6459095 (2002-10-01), Heath et al.
patent: 6465813 (2002-10-01), Ihm
patent: 6472705 (2002-10-01), Bethune et al.
patent: 6525453 (2003-02-01), Cheng et al.
patent: 2001/0023986 (2001-09-01), Mancevski
patent: 2002/0020841 (2002-02-01), Ihm
patent: 2002/0130311 (2002-09-01), Lieber et al.
Choi Won-bong
Lee Jo-won
Lee Young-hee
Everhart Caridad
Lee & Sterba, P.C.
Rocchegiani Renzo
Samsung Electronics Co,. Ltd.
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