Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-08-16
2004-02-24
Nadav, Ori (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S331000, C257S341000, C257S342000
Reexamination Certificate
active
06696726
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to field effect transistors (FETs) and, in particular, to trench double-diffused metal-oxide-semiconductor (DMOS) transistors and methods of fabricating the same.
Power Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) are well known in the semiconductor industry. One type of MOSFET is a double-diffused trench MOSFET, or what is known as a “trench DMOS” transistor. A cross-sectional view of a portion of a typical n-channel trench DMOS transistor
10
is shown in FIG.
1
. It should be pointed out that the relative thickness of the various layers are not necessarily drawn to scale.
The trench DMOS transistor
10
, shown in
FIG. 1
, includes an n-type substrate
100
over which a substrate out-diffusion layer
101
is formed. An n-type epitaxial layer
102
is formed over substrate out-diffusion layer
101
and a p-type body layer
108
covers epitaxial layer
102
. One or more trenches
109
extend through the body layer
108
and a portion of the epitaxial layer
102
. Gate oxide layer
104
lines the sidewalls and bottom of each trench
109
and a conductive material
106
, typically doped polysilicon, lines gate oxide layer
104
and fills each trench
109
. N+ source regions
110
flank each trench
109
and extend a predetermined distance into body layer
108
. Heavy body regions
112
are positioned within body layer
108
, between source regions
110
, and extend a predetermined distance into body layer
108
. Finally, dielectric caps
114
cover the filled trenches
109
and also partially cover source regions
110
. Note that trench DMOS transistor
10
also typically includes one or more metal layers, which contact source regions
110
, with adjacent metal layers separated by an insulating material. These metal layers are not shown in FIG.
1
.
FIG. 2
shows a doping concentration profile, taken along a cross-section labeled “xx” in FIG.
1
. Cross section xx is representative of the resistance path
116
that a drain-to-source current, I
DS
, encounters as charge carriers travel from source region
110
to the drain of trench DMOS transistor
10
, when trench DMOS transistor is on. The various regions that comprise path
116
are source region
110
, body region
108
, epitaxial layer
102
, substrate out-diffusion layer
101
and substrate
100
.
The resistance encountered by I
DS
due to the presence of these various regions is typically quantified as the drain-to-source resistance, R
DS
(on). A high drain-to-source resistance, i.e. R
DS
(on), limits certain performance characteristics of the transistor. For example, both the transconductance, g
m
, of the device, which is a measure of the current carrying capability of the device (given a certain gate voltage) and the frequency response of the device, which characterizes the speed of the device, are reduced the higher R
DS
(on) is. Another factor that limits the speed of the trench DMOS transistor is the gate oxide charge, Q
g
. The higher Q
g
is the larger the gate-to-drain overlap capacitance becomes and, consequently, the lower the switching capability of the device becomes.
Because the drain-source voltage is dropped almost entirely across the channel region, which comprises the body and epitaxial layers, the channel length, channel resistance and channel concentration profile are critical characteristics that affect the operating performance of a trench MOSFET. Whereas the absolute values of these characteristics are important, so too is the controllability of their variation. Wide device-to-device variations negatively affect the reproducibility of a device having desired performance capabilities.
SUMMARY OF THE INVENTION
Generally, according to an exemplary embodiment of the present invention a trench DMOS transistor and its method of manufacture is provided. The trench DMOS transistor is characterized by an ultra-low on resistance (i.e., R
DS
(on)) and a low gate charge. The method of manufacture minimizes variations in the transistor characteristics by controlling out-diffusion from the substrate.
In a first aspect of the invention, a trench DMOS transistor is disclosed. In an exemplary embodiment the trench DMOS transistor comprises a substrate having a first conductivity type that embodies a drain layer of the transistor, the substrate having a substrate doping concentration; a substrate out-diffusion layer formed over the substrate, the substrate out-diffusion layer having a first major surface closest to the substrate that has a doping concentration approximately equal to that of the substrate doping concentration and a second major surface having a lower concentration than the substrate doping concentration; a body region having a second conductivity type, which is epitaxially formed over the substrate; at least one trench having a bottom and sidewalls, each trench extending through the substrate out-diffusion layer and the body region; a dielectric material lining the sidewalls and bottom of the at least one trench; a conductive material lining the dielectric material and substantially filling the trenches; and source regions having the first conductivity type positioned next to each trench within the body region.
In a second aspect of the invention, a substrate cap layer is positioned between the substrate and the substrate out-diffusion layer in the trench DMOS transistor described in reference to the first aspect of the invention.
In a third aspect of the invention, the thickness of the dielectric material at the bottom of the trenches is thicker than a thickness of the dielectric material on the sidewalls of the trenches so that improved gate charge performance is realized.
In a fourth aspect of the invention, a method of fabricating a trench DMOS transistor is disclosed. The method comprises providing a substrate having a first conductivity type that embodies a drain layer of the transistor, the substrate having a substrate doping concentration; forming a substrate out-diffusion layer over the substrate, the substrate out-diffusion layer having a first major surface closest to the substrate that has a doping concentration approximately equal to that of the substrate doping concentration and a second major surface having a lower concentration than the substrate doping concentration; forming a body region having a second conductivity type over the substrate; forming one or more trenches through the substrate out-diffusion layer and the body region, each trench having a bottom and sidewalls; forming a dielectric plug at the bottom of each trench; lining the sidewalls and bottom of each trench with a dielectric material; lining the dielectric material with a conductive material and substantially filling the trenches with the conductive material; and forming source regions having the first conductivity type positioned next to each trench within the body region.
In a fifth aspect of the invention, the dielectric plug described in reference to the fourth aspect of the invention is formed either by high density plasma chemical vapor deposition or sub-atmospheric chemical vapor deposition.
A further understanding of the nature and advantages of the inventions herein may be realized by reference to the remaining portions of the specification and the attached drawings.
REFERENCES:
patent: 4893160 (1990-01-01), Blanchard
patent: 4914058 (1990-04-01), Blanchard
patent: 4941026 (1990-07-01), Temple
patent: 4967245 (1990-10-01), Cogan et al.
patent: 4992390 (1991-02-01), Chang
patent: 5164325 (1992-11-01), Cogan et al.
patent: 5298781 (1994-03-01), Cogan et al.
patent: 5442214 (1995-08-01), Yang
patent: 5689128 (1997-11-01), Hshieh et al.
patent: 5770878 (1998-06-01), Beasom
patent: 5801417 (1998-09-01), Tsang et al.
patent: 5879994 (1999-03-01), Kwan et al.
patent: 5895952 (1999-04-01), Darwish et al.
patent: 6057558 (2000-05-01), Yamamoto et al.
patent: 6191447 (2001-02-01), Baliga
patent: 62-69562 (1987-03-01), None
Technical Literature from Applied Materials, Farhad Moghadam, “Delivering Value Around New Industry Paradigms,” pp
Bencuya Izak
Challa Ashok
Mo Brian Sze-Ki
Fairchild Semiconductor Corporation
Nadav Ori
Townsend and Townsend / and Crew LLP
LandOfFree
Vertical MOSFET with ultra-low resistance and low gate charge does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Vertical MOSFET with ultra-low resistance and low gate charge, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Vertical MOSFET with ultra-low resistance and low gate charge will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3285899