Vertical MOSFET with horizontally graded channel doping

Details Vertical MOSFET with horizontally graded channel doping Vertical MOSFET with horizontally graded channel doping

2002-03-11

2004-05-25

Pham, Long (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S328000, C257S329000

Reexamination Certificate

active

06740920

ABSTRACT:

FIELD OF THE INVENTION
The field of the invention is the formation of vertical transistors in integrated circuit processing.
BACKGROUND OF THE INVENTION
The vertical MOSFET device is advantageous for DRAM scaling (see Li et al, Int. Symp. VLSI Tech. Sys. App. 1999, p251; Radens et al, IEDM 2000, p.349; Gruening et al, IEDM 1999, p.25), since it maintains a desired array MOSFET channel length which is independent of the minimum lithographic feature size elsewhere on the chip. This results in properly scaled array MOSFETs for minimum lithographic feature sizes below 140 nm, which would be unattainable with DRAM arrays employing planar array MOSFETs. The longer channel length of the vertical MOSFET is decoupled from the minimum lithographic feature size, thus not impacting overall density.
Referring now to
FIG. 1
, there is shown a portion of an integrated circuit containing a DRAM cell
80
formed in silicon substrate
10
and including a vertical transistor
100
and a deep trench capacitor
30
. The arrows at the top of the Figure indicate the prior art method of making a laterally uniform implant to adjust the threshold voltage. The implant extends across the entire silicon region that forms the body of the device, so that the dopant concentration is uniform through out the body. A problem known to the art is that a change in the body substrate or p-well bias in the vertical transistor
100
produces a change in the threshold voltage Vt.
In one example, a DRAM having a nominal 110 nm groundrule had a change in Vt of 460 mV in response to a change in P-Well bias from −0.5V to −2.0V and a change of 160 mV for a change in P-well bias from −0.5V to −1.0V. This is an extremely high body effect that causes significant performance degradation for DRAM circuit operating conditions such as write-back, which require charge transfer between bitline and storage capacitor. It would be highly advantageous to find a way to design the vertical device such that the body effect is minimized, but those skilled in the art did not understand the reasons for this high bias sensitivity and consequently were not able to devise an economical solution to this problem.


REFERENCES:
patent: 6025224 (2000-02-01), Gall et al.
patent: 6391705 (2002-05-01), Hsiao et al.
Array Pass Transistor Design in Trench Cell for Gbit DRAM and Beyond Li, et al. VLSI Tech Sys. App. 1999, p. 251.
A Novel Trench DRAM Cell with a Verified Access Transistor and Buried Strap for 4Gb/16Gb, Gruening, et al. IEDM 1999 p. 25.
An Orthogonal 6F&Lgr;2 Trench Sidewall Vertical Device Cell for 4Gb/16Gb DRAM Radens, et al. IEDM 2000, p. 349.

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