Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-03-11
2003-06-03
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S301000, C257S304000, C257S328000, C257S329000, C257S336000
Reexamination Certificate
active
06573561
ABSTRACT:
FIELD OF THE INVENTION
The field of the invention is the formation of vertical transistors in integrated circuit processing.
BACKGROUND OF THE INVENTION
The vertical MOSFET device is advantageous for DRAM scaling (see Li et al, Int. Symp. VLSI Tech. Sys. App. 1999, p251; Radens et al, IEDM 2000, p.349; Gruening et al, IEDM 1999, p.25), since it maintains a desired array MOSFET channel length which is independent of the minimum lithographic feature size elsewhere on the chip. This results in properly scaled array MOSFETs for minimum lithographic feature sizes below 140 nm, which would be unattainable with DRAM arrays employing planar array MOSFETs. The longer channel length of the vertical MOSFET is decoupled from the minimum lithographic feature size, thus not impacting overall density.
Referring now to
FIG. 1
, there is shown a portion of an integrated circuit containing two DRAM cells
80
formed in silicon substrate
10
and disposed on the left and right of the Figure, each cell including a vertical transistor
100
and a deep trench capacitor
30
. A problem known to the art is that the channel length Leff (distance between the drain (node diffusion)
107
and source (bit-line diffusion)
130
(denoted with bracket
134
on the left of the Figure) of the vertical transistor
100
can vary because of fluctuations in the recess etch that opens the aperture that will hold the transistor. Under certain circuit conditions, the transistor will operate such that the source and drain electrodes are switched.
The device recess depth, L-mech, denoted by bracket
136
on the right of the Figure, is defined structurally from scanning electron micrographs (SEM) as the distance from the silicon surface
12
to the bottom of the trench top oxide (TTO)
110
as seen in FIG.
1
. TTO
110
rests on the top of the doped polysilicon
105
that forms the buried strap connecting the drain
107
with the center electrode of the capacitor. Buried strap
105
rests on the top of trench collar
20
that is defined in a timed etch.
In the prior art, the energy of the threshold implant was set such that the concentration peak was midway between source
130
and drain
107
, indicated in the Figure by dashed line
150
. Inevitable fluctuations in the device recess L-mech results in variations of the channel length, thus causing variations in electrical characteristics due to the short channel effects (SCE) in the vertical device. If L-mech gets smaller, Leff
134
of transistor
100
gets smaller, resulting, as those skilled in the art will be aware, in loss of Vt control.
It would be highly advantageous to find a way to design the vertical device such that the fluctuating mechanical length of the channel (the recess control) is not a critical issue for SCE.
SUMMARY OF THE INVENTION
The invention relates to vertical transistors having a structured threshold implant that desensitizes the SCE with respect to fluctuations in the mechanical channel length.
A feature of the invention is the placement of the peak of a Vt implant to one side of the geometric center of the channel and closer to the source (bitline diffusion) than to the drain (node diffusion).
Another feature of the invention is an increase in the dose of the threshold implant to compensate for the boron loss into the bitline diffusion that happens because of the As field effect.
Another feature of the invention is reduced junction leakage when the drain (node diffusion) is maintained at a logic high level.
REFERENCES:
patent: 4967248 (1990-10-01), Shimizu
patent: 5637898 (1997-06-01), Baliga
patent: 6285060 (2001-09-01), Korec et al.
Array Pass Transistor Design in Trench Cell for Gbit DRAM and Beyond Li, et al. VLSI Tech Sys. App. 1999, p. 251.
A Novel Trench DRAM Cell with a Verified Access Transistor and Buried Strap for 4Gb/16Gb, Gruening, et al. IEDM 1999 p. 25.
An Orthogonal 6F2 Trench Sidewall Vertical Device Cell for 4Gb/16Gb DRAM Radens, et al. IEDM 2000, p. 349.
Chidambarrao Dureseti
Divakaruni Ramachandra
Mandelman Jack A.
McStay Kevin
Fenty Jesse A.
Lee Eddie
Petraske Eric W.
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