Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-10-17
2003-09-23
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S329000, C257S331000, C257S339000, C257S341000
Reexamination Certificate
active
06624469
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a vertical MOS transistor having a trench structure.
2. Description of the Related Art
As a discrete power transistor, in recent years, instead of a bipolar transistor, a MOS transistor in which driving power has been improved and the cost has been reduced, comes to be used. Since this power MOS transistor has such a structure that current is made to flow in the direction vertical to a substrate, this is called a vertical MOS transistor, and is frequently used for a case where a large current of, for example, an ampere class is controlled, as an external driver of an IC in a case where a low power consumption and low ON resistance are needed, or the like. In particular, a vertical trench DMOS transistor using a trench structure as shown in
FIG. 3
has a merit that a cell pitch is made minute without increasing a parasitic resistance as compared with a conventional planar type vertical DMOS transistor.
FIG. 2
is a planar type vertical DMOS comprising an N− epitaxial layer
2
on an N+ substrate
1
,gate oxide on the surface of the N− epitaxial layer
2
and a gate electrode
5
on the N− layer
2
, and has a double diffused drain structure.
Then the vertical trench DMOS has been the mainstream as a structure capable of obtaining a small size, low cost, and low ON resistance.
The structure of
FIG. 3
having the trench structure is an example of an N-channel MOS. This structure is formed in such a manner that a semiconductor substrate in which a low concentration N-type layer
2
is epitaxially grown on a high concentration N-type substrate
1
which becomes a drain region, is prepared, a P-type diffusion region
20
called a body region is formed from the surface of this semiconductor substrate by impurity implantation and high temperature heat treatment at 1000° C. or more, and a high concentration N-type impurity region
21
which becomes a source region and a high concentration P-type impurity region
22
for fixing the potential of the body region by ohmic contact are formed from the surface.
For the purpose of making the high concentration N-type impurity region
21
which becomes the source region have the same potential as the high concentration P-type impurity region
22
in
FIG. 3
, a contact layout is adopted, and although not shown, contact of both the regions is made by one contact hole. Then, single crystal silicon is etched through the P-type diffusion region
20
and the high concentration N-type source region
21
to form a silicon trench
23
, and a gate oxide film
4
and a gate electrode
5
made of polycrystalline silicon are embedded in this silicon trench
23
.
By the structure as described above, this structure can be made to function as a vertical MOS transistor in which a current flowing from the rear side high concentration N-type drain region
1
and the low concentration N-type drain region
2
to the surface side high concentration N-type source region
21
is controlled by the gate electrode
5
embedded in the trench
23
through the gate oxide film
4
at the side wall of the trench. A P-channel MOS can be formed by inverting the conductivity type of the diffusion of FIG.
3
.
The structure and manufacturing method of such a vertical MOS transistor are disclosed in, for example, U.S. Pat. No. 4,767,722.
However, in the structure and manufacturing method of such a vertical MOS transistor, there exist problems as follows:
First, the relation between the depth of the trench
23
and the depth of the P-type diffusion region
20
which becomes the body region has a very important influence on the characteristics of the vertical MOS transistor. For example, if the depth of the P-type diffusion region
20
which becomes the body region is deep as compared with the depth of the trench
23
, even if the body region adjacent to the gate oxide film
4
is inverted by the gate electrode
4
, the P-type diffusion region
20
which is not inverted and becomes the P-type body region exists between the inverted channel region and the N-type low concentration drain region
2
, so that a current can not be made to flow between the drain and the source. In the case where the depth of the trench
23
is excessively deeper than the P-type diffusion region
20
which becomes the body region, although this structure can be made to operate as a transistor, an area where the N-type low concentration drain region
2
overlaps with the gate electrode
5
through the gate oxide film
4
becomes large, and the gate-drain capacitance becomes large by this. This capacitance impedes a high frequency operation. Here, although the P-type diffusion region
20
which becomes the body region is formed by diffusing an implanted impurity through the high temperature heat treatment, since fluctuation in a high temperature heat treatment condition is low, fluctuation in the diffusion length is low.
On the other hand, in silicon etching for forming the trench
23
, since there is no indicator used for stopping the etching to a desired etching depth, the etching depth is controlled through a time. However, in an anisotropic dry etching apparatus used here, since an etching rate is fluctuated by changes in apparatus temperature, gas flow rate and distribution, and the like, the total amount of etching, that is, the trench depth is apt to fluctuate. Then, normally, in order to make it possible that the transistor operation can be made even if the depth of the trench
23
becomes shallow because of fluctuation, the amount of etching is set to a valve rather larger than a target value. Thus, the foregoing gate-drain capacitance is redundantly added, and there occurs a limit in the improvement of high frequency operation.
Second, after polycrystalline silicon which becomes the gate electrode
5
is embedded in the trench
23
by CVD, in order to remove other polycrystalline silicon on the surface of the semiconductor substrate except for the polycrystalline silicon in the trench, etch-back of the polycrystalline silicon is carried out. However, if the amount of etch-back is excessively large, the polycrystalline silicon in the trench is slightly etched, and an overlap portion between the polycrystalline silicon region which becomes the gate electrode
5
and the N-type high concentration region
21
disappears, so that a threshold voltage is greatly increased, or in the worst case, the transistor operation is lost.
The etching end time of this polycrystalline silicon is determined by detecting a difference in light emission in plasma when the under layer is exposed as a result of etching of the polycrystalline silicon on the surface of the substrate or by detecting a radical amount in an etching gas, and by adjusting an over etching amount from that. With respect to the etching amount of the polycrystalline silicon at this time, by using the foregoing detecting method, as compared with the silicon etching for forming the trench
23
, although the fluctuation among wafers and lots can be lessened, wafer in-plane fluctuation can not be suppressed. Then, considering that the N-type high concentration source region
21
overlaps with the polycrystalline silicon which becomes the gate electrode
5
to perform the transistor operation even at a place where the etching amount is largest on the wafer surface, the over etching amount of the polycrystalline silicon is determined. Thus, on the wafer surface, there occurs fluctuation in the amount of the overlap between the N-type high concentration source region
21
and the polycrystalline silicon which becomes the gate electrode
5
. A sample in which the overlap amount between the gate and source is large has a large capacitance between the gate and source, so that a trouble is still caused in the high frequency operation.
Third, since the P-type diffusion region
20
which becomes the body region is formed by ion implantation from the principal surface of the N-type epitaxial layer
2
and by the high temperature heat treatment, there is
Adams & Wilks
Loke Steven
Seiko Instruments Inc.
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