Vertical memory cell array and method of fabrication

Details Vertical memory cell array and method of fabrication Vertical memory cell array and method of fabrication

1994-02-22

1996-11-19

Jackson, Jr., Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257321, 257328, 257331, H01L 29788

Patent

active

055765670

ABSTRACT:
A vertical memory cell EPROM array (FIGS. 1, 1a and 1b) uses a vertical floating gate memory cell structure that can be fabricated with reduced cell area and channel length. The vertical memory cell memory array includes multiple rows of buried layers that are vertically stacked --a drain bitline (34) over a source groundline (32), defining a channel layer (36) in between. In each bitline row, trenches (22) of a selected configuration are formed, extending through the drain bitline and channel layer, and at least partially into the source groundline, thereby defining corresponding source (23), drain (24) and channel regions (25) adjacent each trench. The array can be made contactless (FIG. 1a), half-contact (FIG. 2a) or full contact (FIG. 2b), trading decreased access time for increased cell area.

REFERENCES:
patent: 4169291 (1979-09-01), Rossler
patent: 4222062 (1980-09-01), Trotter
patent: 4979004 (1990-12-01), Esquivel
patent: 5017977 (1991-05-01), Richardson
patent: 5021845 (1991-06-01), Hashimoto

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