Vertical load resistor SRAM cell

Details Vertical load resistor SRAM cell Vertical load resistor SRAM cell

1995-08-11

1996-11-26

Crane, Sara W.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257 66, 257347, 257350, 257904, 257903, H01L 2952, H01L 2954, H01L 23522, H01L 23532

Patent

active

055788548

ABSTRACT:
An SRAM cell consisting of a cross coupled transistors, a pair of transfer gate transistors and, a pair of load resistors, loading the cross-coupled transistors. Where soft error immunity is desired, the SRAM cell has a buried oxide layer isolating the devices from the silicon substrate. The load resistor is integrated into a contact stud, connecting a diffusion region of the SRAM cell to a power supply. An opening, in an insulating layer overlying the substrate and in contact with parts of the transistors including some diffusion regions, exposes a selected diffusion region of the SRAM cell. The contact stud with an integral resistor, consists of a core of a conductive material, and a highly resistive thin layer between the conducting core and the sides of the opening in the insulator and the selected contact areas. The conductive layer and the resistive layer are nearly planar with the top of the insulating layer.

REFERENCES:
patent: 4246692 (1981-01-01), Mohan Rao
patent: 4416049 (1983-11-01), McElroy
patent: 4701241 (1987-10-01), Schlesier
patent: 4702937 (1987-10-01), Yamoto et al.
patent: 4727045 (1988-02-01), Cheung et al.
patent: 4755480 (1988-07-01), Yau et al.
patent: 4786612 (1988-11-01), Yau et al.
patent: 4845544 (1989-07-01), Shimizu
patent: 4849248 (1989-07-01), Hashimoto
patent: 4868537 (1989-09-01), Blanchard
patent: 4950620 (1990-08-01), Harrington, III
patent: 4956313 (1990-09-01), Cote et al.
patent: 5030588 (1991-07-01), Hosaka
patent: 5047826 (1991-09-01), Keller et al.
patent: 5049970 (1991-09-01), Tanaka et al.
patent: 5093706 (1992-03-01), Mitsuhashi et al.
patent: 5135882 (1992-08-01), Karniewicz
patent: 5140299 (1992-08-01), Andrews, Jr. et al.
patent: 5159430 (1992-10-01), Manning et al.
patent: 5232865 (1993-08-01), Manning et al.
patent: 5320975 (1994-06-01), Cederbaum et al.
patent: 5381046 (1995-01-01), Cederbaum et al.
patent: 5400277 (1995-03-01), Nowak
patent: 5403772 (1995-04-01), Zhang et al.
D. J. DiMaria, et al, "High Current Injection into SiO.sub.2 from Si rich SiO.sub.2 Films and Experimental Applications" J. Appl. Phys. 51 (5) pp. 2722-2734, May 1980.
M. Kinugawa, et al, "Cell Technology Directions for Advanced MPUs and Other Memory-Embedded Logic Devices" IEEE 1993, IEDM 93-37-93-40.
J. A. Parisi, "Metal Oxide Load for FET Memory Cell" IBM Technical Disclosure Bulletin, V. 14, #6, Nov. 1971, pp. 1745-1746.

Affiliated with

Also associated with

Rating

Vertical load resistor SRAM cell does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Vertical load resistor SRAM cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Vertical load resistor SRAM cell will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1975061