Vertical lead-on-chip package

Details Vertical lead-on-chip package Vertical lead-on-chip package

1992-02-18

1993-08-24

LaRoche, Eugene R.

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Insulating material

257707, 257722, 257723, 257726, H05K 720, H01L 2302

Patent

active

052391990

ABSTRACT:
A vertical lead-on-chip package and the method of making defines a high density array of semiconductor devices with leads extending from and across one face of the device, to the edge of the device such that a plurality of devices are vertically mounted on a circuit board. Each device has a heat sink thereon which is held in a fixture which serves as an array heat sink during testing and burn-in and during mounting and operation of the devices on the circuit board.

REFERENCES:
patent: 3572428 (1971-03-01), Monaco
patent: 4012769 (1977-03-01), Edwards et al.
patent: 4538171 (1985-08-01), Stevens et al.
patent: 4771366 (1988-09-01), Blake et al.
patent: 4803545 (1989-02-01), Birkle
patent: 4872089 (1989-10-01), Ocken et al.
patent: 5016138 (1991-05-01), Woodman
patent: 5019943 (1991-05-01), Fassbenda et al.
Mulligan, "snap-on head exchanger", IBM TDB, vol. 10, No. 8 Jan. 1968, p. 1242.
Dombroski et al., "Thermal conduction stud", IBM TDB, vol. 19, No. 12 May 1977, pp. 4683-4685.

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