Vertical interconnect process for silicon segments

Details Vertical interconnect process for silicon segments Vertical interconnect process for silicon segments

1994-06-23

1997-10-07

Crane, Sara W.

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

257686, 257723, 257777, H01L 2302

Patent

active

056751800

ABSTRACT:
A method and apparatus for vertically interconnecting stacks of silicon segments. Each segment includes a plurality of adjacent die on a semiconductor wafer. The plurality of die on a segment are interconnected on the segment using one or more layers of metal interconnects which extend to all four sides of the segment to provide edge bonding pads for external electrical connection points. After the die are interconnected, each segment is cut from the backside of the wafer using a bevel cut to provide four inwardly sloping edge walls on each of the segments. After the segments are cut from the wafer, the segments are placed on top of one another to form a stack. Vertically adjacent segments in the stack are electrically interconnected by applying electrically conductive epoxy to all four sides of the stack. The inwardly sloping edge walls of each of the segments in the stack provide a recess which allows the electrically conductive epoxy to access the edge bonding pads and lateral circuits on each of the segments once the segments are stacked. The stack of electrically interconnected segments is then mounted below the surface of a circuit board and electrically connected to circuits on the board by applying traces of electrically conductive epoxy between the bonding pads on the top segment of the stack and the circuit board.

REFERENCES:
patent: 3679941 (1972-07-01), Lacombe et al.
patent: 3691628 (1972-09-01), Kim et al.
patent: 3702025 (1972-11-01), Archer
patent: 3769702 (1973-11-01), Scarbrough
patent: 3813773 (1974-06-01), Parks
patent: 3999105 (1976-12-01), Archey
patent: 4300153 (1981-11-01), Hayakawa
patent: 4426773 (1984-01-01), Hargis
patent: 4613891 (1986-09-01), Ng et al.
patent: 4646128 (1987-02-01), Carson et al.
patent: 4659931 (1987-04-01), Schmitz
patent: 4672737 (1987-06-01), Carson et al.
patent: 4677528 (1987-06-01), Miniet
patent: 4706166 (1987-11-01), Go
patent: 4764846 (1988-08-01), Go
patent: 4783695 (1988-11-01), Eichelberger
patent: 4803595 (1989-02-01), Kraus
patent: 4827327 (1989-05-01), Miyauchi et al.
patent: 4835593 (1989-05-01), Arnold et al.
patent: 4894706 (1990-01-01), Sato et al.
patent: 4897708 (1990-01-01), Clements
patent: 4901136 (1990-02-01), Neugebauer et al.
patent: 4907128 (1990-03-01), Solomon
patent: 4941033 (1990-07-01), Kishida
patent: 4954875 (1990-09-01), Clements
patent: 4956694 (1990-09-01), Eide
patent: 4959749 (1990-09-01), Dzarnoski
patent: 4983533 (1991-01-01), Go
patent: 4989063 (1991-01-01), Kolesar, Jr.
patent: 4996583 (1991-02-01), Hatada
patent: 5006923 (1991-04-01), Warren
patent: 5013687 (1991-05-01), Solomon
patent: 5019943 (1991-05-01), Fassbender et al.
patent: 5025306 (1991-06-01), Johnson et al.
patent: 5028986 (1991-07-01), Sugano et al.
patent: 5032896 (1991-07-01), Little et al.
patent: 5055425 (1991-10-01), Leibovitz
patent: 5093708 (1992-03-01), Solomon
patent: 5104820 (1992-04-01), Go et al.
patent: 5111278 (1992-05-01), Eichelberger
patent: 5117282 (1992-05-01), Salatino
patent: 5128831 (1992-07-01), Fox, III et al.
patent: 5135556 (1992-08-01), Hornback
patent: 5138437 (1992-08-01), Kunamoto et al.
patent: 5138438 (1992-08-01), Masayuki
patent: 5172303 (1992-12-01), Bernardoni
patent: 5191404 (1993-03-01), Wu
patent: 5191405 (1993-03-01), Tomita
patent: 5198888 (1993-03-01), Sugano
patent: 5200300 (1993-04-01), Leibovitz
patent: 5202754 (1993-04-01), Bertin
patent: 5221642 (1993-06-01), Burns
patent: 5222014 (1993-06-01), Lin
patent: 5229647 (1993-07-01), Gnadinger
patent: 5231304 (1993-07-01), Solomon
patent: 5247423 (1993-09-01), Lin et al.
patent: 5259110 (1993-11-01), Bross et al.
patent: 5270261 (1993-12-01), Bertin
patent: 5270571 (1993-12-01), Parks et al.
patent: 5283107 (1994-02-01), Bayer et al.
patent: 5309326 (1994-05-01), Minoru
patent: 5311401 (1994-05-01), Gates, Jr. et al.
patent: 5330359 (1994-07-01), Walker
patent: 5434745 (1995-07-01), Shokrgozar et al.
Wojnarowski, R.J., et al. "Three Dimensional Hybrid Wafer Scale Integration Using the GE High Density Interconnect Process," IEEE International Conference on Wafer Scale Integration, Jan. 20, 1993.
Conte, A1 S. "MCM-LThe Answer for Desktop Workstations," ICEMM Proceedings, (1993), pp. 18-21.

Affiliated with

Also associated with

Rating

Vertical interconnect process for silicon segments does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Vertical interconnect process for silicon segments, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Vertical interconnect process for silicon segments will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2359754