Vertical gate transistors in pass transistor logic decode...

Details Vertical gate transistors in pass transistor logic decode... Vertical gate transistors in pass transistor logic decode...

2000-05-30

2001-04-24

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C257S302000, C257S315000

Reexamination Certificate

active

06222788

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates generally to integrated circuits and in particular to vertical gate transistors in pass transistor logic decode circuits.
BACKGROUND OF THE INVENTION
Many decode circuits include multiple transistors arrayed such that a combination of activated transistors produce a logical function. Such transistors in the array are activated, in the case of MOSFET devices, by either applying or not applying a potential to the gate of the MOSFET. This action either turns on the transistor or turns off the transistor. Conventionally, each logical input to the decode circuit is applied to an independent MOSFET gate. Thus, according to the prior art, a full MOSFET is required for each input to the decode circuit. Requiring a full MOSFET for each logic input consumes a significant amount of chip surface area. Conventionally, the size of each full MOSFET, e.g. the space it occupies, is determined by the minimum lithographic feature dimension. Thus, the number of logical functions that can be performed by a given decode circuit is dependent upon the number of logical inputs which is dependent upon the available space to in which to fabricate an independent MOSFET for each logic input. In other words, the minimum lithographic feature size and available surface determine the functionality limits of the decode circuit.
Pass transistor logic is one of the oldest logic techniques and has been described and used in NMOS technology long before the advent of the CMOS technology currently employed in integrated circuits. A representative article by L. A. Glasser and D. W. Dobberpuhl, entitled “The design and analysis of VLSI circuits,” Addison-Wesley, Reading Mass., 1985, pp. 16-20, describes the same. Pass transistor logic was later described for use in complementary pass transistor circuits in CMOS technology. Articles which outline such use include articles by J. M. Rabaey, entitled “Digital Integrated Circuits; A design perspective,” Prentice Hall, Upper Saddle River, N.J., pp. 210-222, 1996, and an article by K. Bernstein et al., entitled “High-speed design styles leverage IBM technology prowess,” MicroNews, vol. 4, no. 3, 1998. What more, there have been a number of recent applications of complementary pass transistor logic in microprocessors. Articles which describe such applications include articles by T. Fuse et al., entitled “A 0.5V 200 mhz 1-stage
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b ALU using body bias controlled SOI pass-gate logic,” Dig. IEEE Int. Solid-State Circuits Conf., San Francisco, pp. 286-287, 1997, an article by K. Yano et al., entitled “Top-down pass-transistor logic design,” IEEE J. Solid-State Circuits, Vol. 31, no. 6, pp. 792-803, June 1996, and an article by K. H. Cheng et al., entitled “A 1.2V CMOS multiplier using low-power current-sensing complementary pass-transistor logic”, Proc. Third Int. Conf. On Electronics, Circuits and Systems, Rodos, Greece, 13-16 Oct., vol. 2, pp. 1037-40, 1996.
In another approach, differential pass transistor logic has been developed to overcome concerns about low noise margins in pass transistor logic. This has been described in an article by S. I. Kayed et al., entitled “CMOS differential pass-transistor logic (CMOS DPTL) predischarge buffer design,” 13th National Radio Science Conf., Cairo, Egypt, pp. 527-34, 1996, as well as in an article by V. G. Oklobdzija, entitled “Differential and pass-transistor CMOS logic for high performance systems,” Microelectronic J., vol. 29, no. 10, pp. 679-688, 1998. Combinations of pass-transistor and CMOS logic have also been described. S. Yamashita et al., “Pass-transistor? CMOS collaborated logic: the best of both worlds,” Dig. Symp. On VLSI Circuits, Kyoto, Japan, 12-14 June, pp. 31-32, 1997. Also, a number of comparisons of pass transistor logic and standard CMOS logic have been made for a variety of different applications and power supply voltages. These studies are described in an article by R. Zimmerman et al., entitled “Low-power logic styles: CMOS versus pass transistor logic,” IEEE J. Solid-State Circuits, vol. 32, no. 7, pp. 1079-1790, July 1997, and in an article by C. Tretz et al., “Performance comparison of differential static CMOS circuit topologies in SOI technology,” Proc. IEEE Int. SOI Conference, Oct. 5-8, FL, pp. 123-4, 1998.
However, all of these studies and articles on pass transistor logic have not provided a solution to the constraints placed on decode circuits by the limits of the minimum lithographic feature size and the deficit in the available chip surface space.
An approach which touches upon overcoming the limits of the minimum lithographic feature size and the deficit in the available chip surface space, is disclosed in the following co-pending, commonly assigned U.S. patent applications by Len Forbes and Kie Y. Ahn, entitled: “Programmable Logic Arrays with Transistors with Vertical Gates,” attorney docket no. 303.683US1, serial number 09/583,584, “Horizontal Memory Devices with Vertical Gates,” Ser. No. 09/584,566, and “Programmable Memory Decode Circuits with Vertical Gates,” Ser. No. 09/584,564. Those disclosures are all directed toward a non volatile memory cell structure having vertical floating gates and vertical control gates above a horizontal enhancement mode channel region. In those disclosures one or more of the vertical floating gates is charged by the application of potentials to an adjacent vertical gate. The devices of those disclosures can be used as flash memory, EAPROM, EEPROM devices, programmable memory address and decode circuits, and/or programmable logic arrays. Those applications, however, are not framed to address overcoming the limits of the minimum lithographic feature size and the deficit in the available chip surface space for purposes of pass transistor logic in decode circuits.
Therefore, there is a need in the art to provide improved transistor decode circuit logic which overcomes these barriers.
SUMMARY OF THE INVENTION
The above mentioned problems with transistor decode circuit logic and other problems are addressed by the present invention and will be understood by reading and studying the following specification. Systems and methods are provided for transistor decode circuit logic having transistors with multiple vertical gates. The multiple vertical gates are edge defined such that only a single transistor is required for multiple logic inputs. Thus a minimal surface area is required for each logic input.
In one embodiment of the present invention, a novel decode circuit is provided. The decode circuit includes a number of address lines and a number of output lines. The address lines and the output lines form an array. A number logic cells that disposed at the intersections of output lines and address lines. According to the teachings of the present invention each logic cell includes a source region and a drain region in a horizontal substrate. A depletion mode channel region separates the source and the drain regions. A number of vertical gates are located above different portions of the depletion mode channel region. At least one of the vertical gates is located above a first portion of the depletion mode channel region and is separated from the channel region by a first thickness insulator material. At least one of the vertical gates is located above a second portion of the channel region and is separated from the channel region by a second thickness insulator material. According to the present invention, there is no source nor drain region associated with each input and the gates have sub-lithographic horizontal dimensions by virtue of being edge defined vertical gates.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, proce

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