Vertical gate transistor with low temperature epitaxial channel

Details Vertical gate transistor with low temperature epitaxial channel Vertical gate transistor with low temperature epitaxial channel

1992-06-17

1994-02-01

Hille, Rolf

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257327, 257329, 257350, H01L 2701, H01L 2976, H01L 2712

Patent

active

052834565

ABSTRACT:
A field effect transistor (FET) with a vertical gate and a very thin channel sandwiched between source and drain layers. In a preferred embodiment of the invention, the FET is formed on a silicon on insulator (SOI) substrate with the silicon layer serving as the first layer (e.g., the source layer). A low temperature epitaxial (LTE) process is used to form a very thin (e.g., 0.1 .mu.m) channel, and a chemically vapor deposited polysilicon layer forms the top layer (e.g., the drain layer). An opening is etched through the three layers to the insulator substrate and its wall is oxidized, forming a gate oxide. Polysilicon is deposited to fill the opening and form the vertical gate.

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patent: 5010386 (1991-04-01), Groover, III
patent: 5072276 (1991-12-01), Malhi et al.
patent: 5140388 (1992-08-01), Bartelink
"Low-temperature silicon epitaxy by ultrahigh vacuum/chemical vapor deposition"; B. S. Meyerson; Appl. Phys. Lett. 48(12), Mar. 24, 1986; IBM T. J. Watson Research Center.

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