Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-02-04
2004-06-08
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S301000
Reexamination Certificate
active
06747306
ABSTRACT:
BACKGROUND
The present invention relates generally to semiconductor memory fabrication and, more particularly, to a vertical gate conductor having a buried contact layer for increased contact landing area, particularly suited for dynamic random access memory (DRAM) cell applications.
A dynamic random access memory (DRAM) circuit generally includes an array of memory cells interconnected by rows and columns, which are known as wordlines (WLs) and bitlines (BLs), respectively. Reading data from or writing data to memory cells is achieved by activating selected wordlines and bitlines. Typically, a DRAM memory cell includes a MOSFET (metal oxide semiconductor field effect transistor) connected to a storage capacitor for storing a bit of information. The MOSFET (also referred to as an access transistor, since it provides access by the bitline to the storage capacitor) includes a gate, as well as diffusion regions which are referred to as either drain or source regions, depending on the operation of the transistor.
Trench capacitors are one type of storage capacitor commonly used in DRAM cells. Specifically, a trench capacitor is a three-dimensional structure formed by etching trenches of various dimensions into a silicon substrate. Trenches typically include N+ doped polysilicon as one plate or electrode of the capacitor (i.e., the storage node). The other plate of the capacitor is formed usually by diffusing N+ dopants out from a dopant source into a portion of the substrate surrounding the lower part of the trench (i.e., a buried plate). A node dielectric is also formed along the lower walls of the trench, between the storage node and the buried plate, thereby forming the storage capacitor.
In order to prevent carriers from traveling through the substrate between the adjacent devices, device isolation regions are formed between adjacent semiconductor devices. Generally, such device isolation regions take the form of thick oxide regions extending below the surface of the semiconductor substrate. A sharply defined trench is formed in the semiconductor substrate by, for example, anisotropic etching. The trench is then filled with oxide back to the surface of the substrate to provide a device isolation region. Trench isolation regions thus formed are called shallow trench isolation (STI) and have the advantages of providing device isolation regions across their entire lateral extent and of providing a more planar structure.
There are different types of MOSFET structures that have been used in conjunction with DRAM cells. For example, a planar MOSFET is a transistor wherein the channel region of the transistor is generally parallel to the primary surface of the substrate. However, as course of DRAM development continues to be driven by the need for smaller cell sizes, vertical MOSFETs have emerged as the device of choice is in scaling the array transistor. A vertical MOSFET is a device built along the walls of a trench (i.e., the upper portion of the deep trench that is also used to construct the storage capacitor), such that the channel region of the transistor is generally perpendicular to the primary surface of the substrate. Thus, vertical MOSFETs allow the bit densities needed for effective size reduction. However, since the use of vertical MOSFETs is not yet widespread, there are several processing difficulties that need to be addressed.
For example, in forming a contact from a bitline to the bitline diffision of a cell through a conductive stud (e.g., polysilicon), care is taken align the stud over the active area (AA) landing area, but also to do so without shorting the stud with the gate contact (i.e., avoiding wordline to bitline shorts). However, as the cell size and deep trench diameters continue to shrink, the critical overlay and critical dimension requirements of photolithographic patterning result in less margin for error in landing the bitline contacts. Accordingly, it would be desirable to be able to increase the effecting landing area for borderless bitline contacts in a manner that easily integrates with existing gate top engineering and top oxide methods.
SUMMARY
The foregoing discussed drawbacks and deficiencies of the prior art are overcome or alleviated by an access transistor for a semiconductor device. In an exemplary embodiment, the transistor includes a gate disposed in an upper region of a deep trench formed within a substrate of the semiconductor device. A gate contact is formed atop the gate, the gate contact having a diameter less than that of the deep trench and the gate. A conductive layer surrounds the gate contact, the conductive layer being disposed over the deep trench and over an active area of the semiconductor device surrounding the deep trench. The conductive layer provides a effective contact landing area for a diffusion region formed in the active area, wherein the effective contact landing area further includes a region between the diffusion region and the gate contact.
In another aspect, a memory cell for a dynamic random access memory (DRAM) array includes a storage capacitor formed within a lower region of a deep trench, and a vertical access transistor coupled with the storage capacitor. The vertical access transistor further includes a gate disposed in an upper region of the deep trench, a gate contact formed atop the gate, the gate contact having a diameter less than that of the deep trench and the gate, and a conductive layer surrounding the gate contact. The conductive layer is disposed over the deep trench and over an active area of the semiconductor device surrounding the deep trench, wherein the conductive layer provides a effective contact landing area for a bitline diffusion formed in said active area. The effective contact landing area further includes a region between the bitline diffusion and the gate contact.
REFERENCES:
patent: 4689871 (1987-09-01), Malhi
patent: 5077228 (1991-12-01), Eklund et al.
patent: 5140388 (1992-08-01), Bartelink
patent: 5293053 (1994-03-01), Malhi et al.
patent: 5324973 (1994-06-01), Sivan
patent: 5482883 (1996-01-01), Rajeevakumar
patent: 5574299 (1996-11-01), Kim
patent: 5583075 (1996-12-01), Ohzu et al.
patent: 5740068 (1998-04-01), Kiebmann et al.
patent: 6037202 (2000-03-01), Witek
patent: 6096596 (2000-08-01), Gonzalez
patent: 6175953 (2001-01-01), Scepanovic et al.
patent: 6269472 (2001-07-01), Garza et al.
patent: 62118567 (1987-05-01), None
patent: 3133173 (1991-06-01), None
Cantor & Colburn LLP
Capella Steven
Ngo Ngan V.
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