Vertical field effect transistor with an extended polysilicon ch

Details Vertical field effect transistor with an extended polysilicon ch Vertical field effect transistor with an extended polysilicon ch

1991-05-08

1993-01-19

James, Andrew J.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257332, 257334, H01L 2910

Patent

active

051810883

ABSTRACT:
An MOS FET of the semiconductor device includes a semiconductor substrate on which a projection is formed via a given film. The projection is made of a polysilicon having grain boundaries. A pair of gate electrodes are provided so that one of the gate electrodes faces the other thereof via side walls of the projection and gate oxide films. A conductive channel forming area is formed at the side walls of the projection, so that the extending direction of the channel is parallel to the thickness direction of the substrate.

REFERENCES:
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patent: 4554570 (1985-11-01), Jastrzebski et al.
patent: 4554572 (1985-11-01), Chatterjee
patent: 4670768 (1987-06-01), Sunami et al.
patent: 4672410 (1987-06-01), Mikata
patent: 4920397 (1990-04-01), Ishijima
patent: 4937641 (1990-06-01), Sunami et al.
patent: 4951102 (1990-08-01), Beitman et al.
patent: 5001540 (1991-03-01), Ishihara
Patent Abstracts of Japan, vol. 7, No. 200 (E-196) [1345], Sep. 3, 1983; Japanese Patent Publication No. 58-97868, dated Jun. 10, 1983, Yoshioka.
Patent Abstracts of Japan, vol. 10, No. 340 (E-455)[2396], Nov. 18, 1986; Japanese Patent Publication No. 61-144875, dated Jul. 2, 1986, Ebihara.

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