Vertical field effect transistor

Details Vertical field effect transistor Vertical field effect transistor

2003-05-27

2004-05-11

Lee, Eddie (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S263000, C257S331000, C257S332000, C257S333000, C257S334000

Reexamination Certificate

active

06734494

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention The present invention relates to a vertical field effect transistor provided with a trench-gate structure and having a current path along the sidewall of trench in a direction of thickness of substrate.
2. Description of the Related Art
Conventionally, a field effect transistor (hereinafter, referred to as MOS transistor) has been employed as one of power devices designed to withstand relatively high current densities and the application of relatively high voltages. Since the MOS transistor is the device of the type used to control its operation by means of voltage, it is advantageously able to operate without need for current input to the transistor to control its operation. Furthermore, the MOS transistor operates utilizing the lateral flow of carriers as a majority carrier that is the only one selected from an electron and a hole. On the other hand, a bipolar transistor operates utilizing the flow of the minority carriers in a vertical direction. Moreover, the bipolar transistor is forced to operate at lower speed when minority carriers accumulates within a base formed extremely thin in a vertical direction. The MOS transistor never suffers from the aforementioned undesirable accumulation of carriers. Accordingly, the MOS transistor is able to switch its state between ON and OFF at high speed. Furthermore, since the MOS transistor has a source and a drain spaced from each other by a distance longer compared with the length of base of bipolar transistor, the MOS transistor operates in a punch-through mode less potentially than the bipolar transistor. Therefore, the MOS transistor has frequently been employed as an inductive load such as a switching regulator.
The first a MOS transistor which became commercially availablewas of the type that allows operation current (drain current) to flow in a direction (lateral direction) parallel to the principal surface of a semiconductor substrate. In contrast, recently, a vertical MOS transistor has been widely used which allows drain current to flow in a direction (vertical direction) vertical to the principal surface of a semiconductor substrate. The vertical MOS transistor can advantageously increase its current capacity because the transistor can be designed to arrange a number of unit cells as a unit element in parallel with one another, constituting a MOS transistor.
For a power device designed to withstand high current densities and the application of high voltages, the on-state series resistance (hereinafter, referred to as on-resistance) and the off-state blocking voltage are important. Since the on-resistance largely affects the switching operation of the power device, the on-resistance is desirably made as small as possible. Furthermore, the off-state blocking voltage is desirably made as large as possible so as to enable the power device to withstand the application of high voltages. Therefore, for making the best of the aforementioned advantages, the vertical MOS transistor needs to reduce its on-resistance and to improve off-state blocking voltage.
FIG. 1
is a cross-sectional view of an example of a conventional vertical MOS transistor. As shown in
FIG. 1
, the vertical MOS transistor includes: an N.sup.+(heavily N-type doped) substrate
101
; an N.sup.−(lightly N-type doped) layer
102
, a P-type base layer
103
; an N.sup.+source region
104
; a trench
105
; a gate insulating film
106
; a gate electrode
107
; an interlayer insulating film
108
; a source electrode
109
; a drain electrode
110
; and a channel region
111
. Furthermore, in the figure, L denotes spacing between trenches.
The vertical MOS transistor having the aforementioned configuration operates as follows. A specific drain voltage V.sub.DS is applied between the source electrode
109
and the drain electrode
110
, and a specific gate voltage V.sub.GS is applied between the source electrode
109
and the gate electrode
107
. Then, the channel region
111
of the P-type base layer
103
in the vicinity of the gate insulating film
106
is inverted to form an N-type region which is a channel that allows electric charges to flow therethrough. The inverted channel provides electrical connection between the source and drain of the transistor. At this point, the resistance between the source and drain is referred to as an on-resistance of the vertical MOS transistor.
Additionally, when the channel region between source and drain is being electrically conductive (in an on-state), the gate voltage V.sub.GS applied between the source electrode
109
and the gate electrode
107
is set to 0 volts or to a negative voltage, i.e., a reverse bias. This turns off the gate and turns the inverted channel region
111
back to a P-type region, turning an electrical path between source and drain to a nonconductive state (i.e., off-state). Thus, controlling the gate voltage V.sub.GS allows control of current flow between source and drain, and further allows the vertical MOS transistor to be employed as a power switch element.
The off-state blocking voltage BV.sub.DS of the vertical MOS transistor is defined as a drain voltage V.sub.GS that can be applied to the transistor whose gate is in an off-state. The voltage BV.sub.DS is generally determined by the dopant concentration and the thickness of the N.sup.−layer
102
. However, in case of a vertical MOS transistor, the voltage BV.sub.DS further depends on how the surface region of the transistor is constructed. Particularly, in case of a vertical field effect transistor with a trench-gate structure, since the trench
105
penetrates the P-type base layer
103
and then protrudes into the N.sup.−layer
102
, the blocking voltage BV.sub.DS of the transistor is determined by the distal end of the trench
105
protruding into the N.sup.−layer
102
.
FIG. 2
is an electrical field contour plot showing simulated equipotential line distributions representing individual electric potentials of regions that range from the central portion of trench to the central portion of cell and are located around the distal end of trench in the vertical MOS transistor shown in FIG.
1
. In this case, the conditions employed to determine the simulated equipotential line distributions are as follows. That is, dopant concentration of the N.sup.−layer
102
is 1 ohm-cm and total vertical thickness of the P-type base layer
103
and the N.sup.−layer
102
is 8.5 micrometers.
As can be seen from
FIG. 2
, when a drain voltage V.sub.DS is applied to the vertical MOS transistor, a depletion zone extends from the P-type base layer
103
to the N.sup.−layer
102
. However, an equipotential line representing a higher potential below the boundary between the layers
103
,
102
and located in the vicinity (denoted by “C” in
FIG. 2
) of the corner of the distal end of the trench
105
protruding into the N.sup.−layer
102
is pulled a little in a direction approaching the adjacent and lower potential line, increasing the strength of an electric field in the vicinity of the corner. Thus, the strength of an electric field in the vicinity of the corner determines the blocking voltage of transistor, voltage is lower than that of a transistor having no protrusion of the trench
105
into the N.sup.−layer
102
.
To prevent lowering of the blocking voltage of a vertical MOS transistor having a trench-gate structure, for example, a vertical MOS transistor disclosed in U.S. Pat. No. 5,072,266 is proposed.
FIG. 3
is a perspective cross-sectiona lview of the vertical MOS transistor disclosed in U.S. Pat. No. 5,072,266. The vertical MOS transistor shown in
FIG. 3
has a heavily doped P-type region provided in the central portion of a P-type base layer
103
and having a depth larger than that of a trench
105
. The remaining configuration of the vertical MOS transistor shown in
FIG. 3
is the same as that of the conventional vertical MOS transistor.
Additionally, Japanese Patent Application Laid-open No. 8(1996)-167711 discloses a vertical MOS

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