Vertical field-effect semiconductor device with buried gate...

Details Vertical field-effect semiconductor device with buried gate... Vertical field-effect semiconductor device with buried gate...

2001-04-05

2003-07-29

Le, Vu A. (Department: 2824)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S077000, C438S268000

Reexamination Certificate

active

06600192

ABSTRACT:

TECHNICAL FIELD
The present invention relates to an improvement of a field effect semiconductor device.
BACKGROUND ART
As a vertical type power semiconductor device having a small input loss, being excellent in high speed switching characteristics, and having a high input impedance, for example, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is known.
FIG. 8
is a cross-sectional view of a trench gate type MOSFET of a prior art. In this trench gate type MOSFET of the prior art, by employing a trench type structure forming a gate
106
in a recess
110
, an efficient utilization of the surface area is intended; and it is intended to reduce power loss. Recently, a power semiconductor device using a single crystal material of silicon carbide (SiC) has been produced by way of trial; and as for the trench gate type MOSFET of
FIG. 8
, an n-type drift layer
102
is formed on a semiconductor substrate
101
of an n-type silicon carbide by epitaxial method. A p-type body layer
103
is formed on the n-type drift layer
102
, and in addition, an n-type source region
104
is formed in a predetermined region of the p-type body layer. The recesses
110
are formed at both the end parts of the n-type source region
104
and the p-type body layer
103
so as to reach the n-type drift layer
102
, and gate electrodes
106
are formed via respective gate insulating films
105
formed on the surface of the recesses
110
. A source electrode
108
is formed on the p-type body layer
103
and the n-type source regions
104
. A drain electrode
107
is formed on the bottom surface of the n-type silicon carbide semiconductor substrate
101
.
A voltage is applied to the gate electrode
1061
and an electric field is given to the gate insulating films
105
of the recess parts placed between the gate electrodes
106
and the p-type body layer
103
of the recess sidewall part, and thereby, the conductive type of the p-type body layer
103
which contacts the gate insulating film
105
is inverted to the n-type so as to form a channel which makes the carriers flow between the source S and the drain D.
FIG. 9
is a cross-sectional view of an ACCUFET (accumulation field effect transistor: see IEEE Electron Device Letters, vol. 18, No. 12, December 1997) which uses SiC according to another prior art. In the ACCUFET, a p+-type buried region
109
is formed by injecting ions into a drift layer
102
. This buried region
109
is connected to a source region
104
with a connection wire
115
so as to be at the same potential as the source region
104
, and thereby, an electric field at the lower part of the gate insulating film
105
is alleviated. By making the buried region
109
and the source region
104
identical in potential, a depletion layer expands in a channel part
111
due, to the existence of a built-in voltage of the junction, and without applying a gate voltage to the gate G, a normally off operation becomes possible, so as to interrupt a current between the drain,D and the source S, and in addition, it becomes advantageous to heighten a withstand voltage.
In the vertical type semiconductor device which has the trench structure of the trench gate type MOSFET, or the like, in
FIG. 8
, when it is intended to heighten a withstand voltage, electric field tends to concentrate at the bottom parts or at the corner parts of the trench
110
, therefore, it is difficult to heighten the withstand voltage. Particularly in a semiconductor device using SiC, since the insulation breakcdown electric field is high, the impurity density of the drift layer
102
can be made high so as to lower the resistance thereof. As a result, the electric field in the vicinity of the gate insulating film
105
at the bottom part of the trench
110
becomes higher and it is difficult to heighten the withstand voltage. In addition, though it is necessary to make the gate voltage high in order to implement a low ON-state resistance, when a high gate voltage is applied, the electric field in the vicinity of the gate insulating film
105
becomes high so as to lower the reliability of the device.
Moreover, in the vertical type semiconductor device which has the trench structure, because of the influence of the process for forming the trench
110
, the interface state density which exists at the interface between the gate insulating film
105
and the drift layer
102
becomes large and the roughness of the interface becomes greater. Because of that influence, the mobility of the channel which is a current path in ON-state becomes small and, as a result, an ON-state resistance becomes large.
In an ACCUFET semiconductor device or the like, which does not have the trench structure of
FIG. 9
, since no trenches are formed, the interface state density is not large and, the influence of the roughness of the interface is small unlike in a semiconductor device of a trench structure. In addition, in the case that a high voltage is applied to the drain D at OFF-state, a depletion layer expands from the p+-buried region
109
to the side of the drain electrode
107
, bringing the area between the buried region
109
and the drift layer into a pinch off state thereby to withstand a high voltage, and therefore, a high electric field is not applied to the gate insulating film
105
. In order to maintain the normally OFF-state, that is to say, the OFF-state even when the drain voltage is 0 V in this structure, however, it is necessary to bring the channel region
111
into a pinch off state by means of a depletion layer formed by the built-in voltage in the junction part between the buried region
109
and the channel
111
located above. Therefore, the channel width of the channel region
111
has to be narrow. On the other hand, in order to realize a low ON-state resistance at the ON-state, the width of the channel needs to be made wider, and therefore, it is difficult to realize both the maintenance of the normally OFF-state and the low ON-state resistance at the ON-state.
DISCLOSURE OF THE INVENTION
The present invention purposes to provide a semiconductor device which alleviates the electric field at the lower parts of the gate insulating film
105
, being low in an ON-state resistance, high in a withstand voltage and high in reliability.
In a semiconductor device of the present invention, a channel region of the first conductive type of a low impurity density comprising a source region of the first conductive type of a high impurity density is formed so as to contact, except for a portion of the bottom part thereof, a buried gate region, a buried gate contact region and a surface gate contact region of the second conductive type. In addition, it has the configuration wherein a gate electrode is provided so as to face said channel region between the source region of the first conductive type and the surface gate contact region of the second conductive type via an insulating film.
According to the configuration-, when a voltage equal to or below the built-in voltage of the junction is applied to the gate electrode at the ON-state, the depletion layer expanding into the above-mentioned channel region contracts into a narrow range of the channel region. Therefore, the channel width through which a current flows becomes wide so that a low ON-state resistance is realizable at a low gate voltage.
At the OFF-state, a depletion layer expands from the junction of the buried gate region as well as the buried gate contact region of the second conductive type and the drift layer, to the side of the drain so as to pinch off the area between both of the buried regions and support a voltage and, therefore, a high electric field is not applied to the gate insulating film and a semiconductor device of a high reliability is obtainable.
In addition, in an area between the buried gate region of the second conductive type and the buried gate contact region of the second conductive type, in order to maintain the ON-state resistance at a low value and to reduce the gate resistance, buried gate connection regions of the second con

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