Vertical channels in split-gate flash memory cell

Details Vertical channels in split-gate flash memory cell Vertical channels in split-gate flash memory cell

1999-05-24

2000-06-20

Thomas, Tom

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257316, 257315, 257314, 438594, 438259, H01L 29788

Patent

active

060780762

ABSTRACT:
A method of forming a vertical memory split gate flash memory device on a silicon semiconductor substrate is provided by the following steps. Form a floating gate trench hole in the silicon semiconductor substrate, the trench hole having trench surfaces. Form a tunnel oxide layer on the trench surfaces, the tunnel oxide layer having outer surfaces. Form a floating gate electrode layer filling the trench hole on the outer surfaces of the tunnel oxide layer. Form source/drain regions in the substrate self-aligned with the floating gate electrode layer. Pattern the floating gate electrode layer by removing the gate electrode layer from the drain region side of the trench hole Form a control gate hole therein. Form an interelectrode dielectric layer over the top surface of the floating gate electrode, and over the tunnel oxide layer. Form a control gate electrode over the interelectrode dielectric layer over the top surface of the floating gate electrode and extending down into the control gate hole in the trench hole.

REFERENCES:
patent: 5045490 (1991-09-01), Esquivel et al.
patent: 5313421 (1994-05-01), Guterman et al.
patent: 5467305 (1995-11-01), Bertin et al.
patent: 5595927 (1997-01-01), Chen et al.
patent: 5786612 (1998-07-01), Otani et al.

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