Vertical channel transistor in semiconductor device and...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S328000, C257SE27057, C257SE27096

Reexamination Certificate

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07851842

ABSTRACT:
A method of fabricating a vertical channel transistor for a semiconductor device includes forming, on a substrate, a plurality of active pillars each having a gate electrode formed on and surrounding a lower portion thereof; forming a first insulation layer over the active pillars to fill a gap region between the active pillars; partially removing the first insulation layer to exposes a circumferential surface of the gate electrode in all directions, without exposing the substrate in the gap region between the active pillars; forming a conductive layer on the remaining first insulation layer to fill the gap region between the active pillars; and patterning the conductive layer to form a word line that surrounds and contacts the circumferential surface of the gate electrode in all directions.

REFERENCES:
patent: 6104061 (2000-08-01), Forbes et al.
patent: 6150688 (2000-11-01), Maeda et al.
patent: 7531412 (2009-05-01), Yoon et al.
patent: 1020060041415 (2006-05-01), None
patent: 100660881 (2006-12-01), None
patent: 1020070038233 (2007-04-01), None
Korean Notice of Allowance for application No. 10-2008-0027425, citing the attached reference(s).
Korean Office Action for application No. 10-2008-0027425, citing the attached reference(s).

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