Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Field effect transistor
Reexamination Certificate
2000-06-15
2001-11-06
Munson, Gene M. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Field effect transistor
C257S191000, C257S316000, C257S616000
Reexamination Certificate
active
06313487
ABSTRACT:
CROSS-REFERENCES TO RELATED APPLICATIONS
This patent application is related to copending application Serial No. 04/595,366 filed concurrently herewith, for FLOATING GATE TRANSISTOR HAVING BURIED STRAINED Si-Ge CHANNEL LAYER.
BACKGROUND OF THE INVENTION
This invention relates generally to insulated gate field effect transistors (IGFET) and metal oxide silicon transistors (MOSFET), and more particularly the invention relates to such transistors having a floating gate for use in electrically erasable, programmable read only memory (EEPROM) cells and flash EEPROM cells.
The MOSFET transistor has source and drain regions separated by a channel region with the conduction of the channel region controlled by voltage biasing an overlying control gate. The flash EEPROM device has the structure of a MOSFET but includes an electrically isolated gate, or floating gate, between the control gate and the channel region for storing charge. Controlling the amount of charge on the floating gate alters the threshold voltage and creates a nonvolatile memory function. Flash memory development is therefore driven by some of the same concerns as MOS technology, but in addition to the demands for scalable devices with high access times and low leakage currents it adds to the requirement of efficient, controllable gate currents and channel hot electron (CHE) programming as used in conventional flash cells. However, as the drain and gate voltages are lowered the CHE programming becomes less efficient.
Another concern for both flash memories and MOSFET devices is the challenge of defining planar features, especially channel lengths at smaller dimensions. To overcome the limitations of determining the channel length by lithographic methods, vertical channel devices have been proposed in which the channel is formed on the sidewall of a trench, mesa or pillar. The length of the channel is then determined by epitaxial layer growth or etch rates in the devices.
Since flash memory is used mostly in mobile applications, low power operation is desirable. For programming with lower drain and gate voltages, a negative substrate voltage may be applied that produces a different programming mechanism that is more effective than the CHE programming at the lower voltages. Channel initiated secondary electron (CHISEL) injection occurs when a substrate bias is applied, and the mechanism is also known as substrate current induced hot electron (SCHE) injection. Channel electrons gain energy as they travel to the drain and produce primary impact ionization. The holes generated in the drain then travel back across the drain junction and gain energy as they pass through the depletion region where they can produce a secondary impact ionization (SII). The secondary electrons created by SII can travel back to the Si-SiO
2
interface and be injected into the floating gate.
The present invention is directed to a flash memory cell and EEPROM device having a vertical channel and employing channel initiated secondary electron injection for programming.
SUMMARY OF THE INVENTION
In accordance with the invention a field effect transistor comprises a semiconductor body with source and drain regions separated vertically by a channel region comprising a Si
x
Ge
1−x
layer. The device is fabricated by epitaxially growing a silicon germanium alloy layer on a silicon substrate, and then growing a layer of silicon on the silicon germanium alloy layer to form a heterojunction with the alloy layer. A trench, mesa, pillar or like structure is then formed by etching to expose a sidewall of the silicon germanium layer. A gate dielectric is grown or deposited on the sidewall, and a floating gate material is then deposited and patterned. An inter-gate dielectric is then grown or deposited, and a source and drain are formed such as by ion implantation. A control gate is then formed on the inter-gate dielectric over the floating gate.
In preferred embodiments, the epitaxial silicon germanium layer is compressively strained with the mole fraction, 1−x, either uniform or graded. A silicon layer can be epitaxially grown on the sidewall and function as a cap layer for the channel.
The heterojunction of the vertical channel enhances secondary electron injection due to the smaller Si—Ge bandgap, thus requiring less energy in creating electron-hole pairs. Further, holes generated by primary impact ionization in the drain and traveling toward the substrate gain additional energy from the valence band offset at the heterostructure interface and therefore are more likely to produce a greater amount of secondary ion injection closer to the silicon-silicon oxide surface. The silicon germanium layer also helps by producing a heterostructure that redirects the flow of the substrate current away from the source junction, and thus avoids a bipolar-type breakdown that occurs when holes of the substrate current are injected into the source region.
The invention and objects and features thereof will be more readily apparent from the following detailed description and appended claims when taken with the drawing.
REFERENCES:
patent: 4499557 (1985-02-01), Holmberg et al.
patent: 4599705 (1986-07-01), Holmberg et al.
patent: 4870470 (1989-09-01), Bass, Jr. et al.
patent: 5162880 (1992-11-01), Hazama et al.
patent: 5272365 (1993-12-01), Nakagawa
patent: 5334855 (1994-08-01), Moyer et al.
patent: 5341328 (1994-08-01), Ovshinsky et al.
patent: 5349209 (1994-09-01), Moyer et al.
patent: 5432356 (1995-07-01), Imamura
patent: 5451800 (1995-09-01), Mohammad
patent: 5534712 (1996-07-01), Ovshinsky et al.
patent: 5534713 (1996-07-01), Ismail et al.
patent: 5546340 (1996-08-01), Hu et al.
patent: 5659504 (1997-08-01), Bude et al.
patent: 5698869 (1997-12-01), Yoshimi et al.
patent: 5801396 (1998-09-01), Chan et al.
patent: 5818761 (1998-10-01), Onakado et al.
patent: 5821136 (1998-10-01), Chan et al.
patent: 5821577 (1998-10-01), Crabbe et al.
patent: 5901084 (1999-05-01), Ohnakado
patent: 5926414 (1999-07-01), McDowel et al.
patent: 5969384 (1999-10-01), Hong
patent: 5986581 (1999-11-01), Magdaleno, II et al.
patent: 5991200 (1999-11-01), Seki et al.
patent: 6013950 (2000-01-01), Nasby
patent: 6031263 (2000-02-01), Forbes et al.
patent: 6204123 (2001-03-01), Mori
patent: 6207978 (2001-03-01), Fastow
Banerjee Sanjay K.
Kencke David L.
Board of Regents , The University of Texas System
Munson Gene M.
Townsend and Townsend / and Crew LLP
Woodward Henry K.
LandOfFree
Vertical channel floating gate transistor having silicon... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Vertical channel floating gate transistor having silicon..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Vertical channel floating gate transistor having silicon... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2614611