Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-08-03
2001-07-31
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S321000, C438S192000
Reexamination Certificate
active
06268621
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to a vertical channel field effect transistor and to a process for manufacturing the transistor. More particularly, the present invention relates to a vertical channel field effect transistor having a short channel length and to a process of manufacturing such a structure.
BACKGROUND OF THE INVENTION
The integrated circuit industry continues to explore techniques to pack more circuits onto a given semiconductor substrate. Accordingly, more and more thought is being devoted to orienting the various devices in planar fashion along the surface of the substrate. Thought is also being devoted to orienting the devices vertically either by building devices “up” from the substrate surface or by burying devices in trenches formed within the face of the semiconductor body.
Currently, a majority of circuits and memory chips are fabricated using metal-oxide semiconductor field effect transistor (MOSFET) technology. This technology places conventional horizontal MOSFET circuits having a source and drain at the same level on the substrate. With appropriate voltage adjustments, the circuits can be reduced in area simply by scaling to smaller dimensions. Specifically, all dimensions of the various process masks can be uniformly reduced so that the resulting circuitry is fabricated in a smaller area on the semiconductor wafer. Unfortunately, the process of scaling down a MOSFET circuit presents certain difficulties.
Reduction of the channel length has been the single biggest variable in reducing the dimensions of field effect transistors. Conventional horizontal field effect transistors rely on the capability of photolithographic tools to define the channel length. Therefore, the performance of conventional field effect transistors is limited by the capability of the available photolithographic tools. As of 1999, the photolithographic limit on the channel length is about 0.15 microns (1,500 angstroms).
In addition to reducing the field effect transistor dimensions, reduction of the channel length offers performance advantage. In thin film field effect transistors, the device output currents and high speed are dependent on the length of the semiconductor conduction channel formed between the source electrode and the drain electrode under the influence of the gate electrode. The source-to-drain output current is inversely proportional to the channel length, while the operating frequency is inversely proportional to the square of the channel length. Thus, when the channel length of the device is reduced by an order of magnitude, for example from 2 to 0.2 microns, the output current should increase 10 fold and the operating speed or frequency increases approximately 100 fold.
The operating speed also depends on the interelectrode capacitance of the device; a large capacitance causes slower operation. The extension of the gate electrode over the source and drain electrodes is a common source of interelectrode capacitance, and is referred to as “overlap” parasitic capacitance. The overlap is a result of limited photolithographic resolution.
Large area arrays of multiple thin film field effect transistors may be prepared by standard 0.2 micron photolithography. When so prepared, the minimum channel length that can be achieved in planar thin film transistor arrays is limited by photolithographic feature and is typically on the order of 0.2 microns as of 1999. One way to overcome the limitations inherent in large area photolithographic resolution is to use a vertical structure in which channel length is determined by vertical separation of the source and drain electrodes.
There remains a need for a field effect transistor design capable of achieving short channel length and faster operation that is not constrained by photolithographic limits. Therefore, an object of the present invention is to provide a vertical channel FET having reduced dimensions as compared to conventional field effect transistors, particularly a reduced channel length between the source and drain. A related object is to provide a vertical channel FET that is not constrained by photolithographic limits. Another object is to provide a vertical channel FET having relatively fast operation. Still another object of the present invention is to overcome the shortcomings of conventional field effect transistors. Other objects and advantages will become apparent from the following detailed description.
SUMMARY OF THE INVENTION
To achieve this and other objects, and in view of its purposes, the present invention provides a vertical channel field effect transistor disposed on a surface of a substrate. The vertical channel field effect transistor comprises an epitaxial silicon stack having a bottom terminal comprising heavily doped silicon, a channel comprising lightly doped silicon of opposite doping type from the bottom terminal, and a top terminal comprising heavily doped silicon of the same doping type as the bottom terminal. The bottom terminal and top terminal are wired such that one is the source and the other is the drain of the field effect transistor, depending on the particular use of the field effect transistor. The vertical channel field effect transistor also comprises a gate dielectric layer covering at least a portion of the top terminal, the channel, and the bottom terminal, and a gate in contact with the gate dielectric layer. The gate is positioned adjacent the channel and adjacent at least a portion of the bottom terminal and top terminal. The channel has a thickness between the bottom terminal and the top terminal from about 50 angstroms to about 800 angstroms. Preferably, the thickness of the channel is from about 100 angstroms to about 500 angstroms.
According to a further aspect of the present invention, there is provided a process of manufacturing a vertical channel field effect transistor. The process comprises forming a mask on a substrate surface, the mask having an epitaxial silicon stack trench extending to the substrate surface. Next, an epitaxial silicon stack is formed on the substrate surface, the epitaxial silicon stack having a bottom terminal comprising heavily doped silicon, a channel comprising lightly doped silicon of opposite doping type from the bottom terminal, and a top terminal comprising heavily doped silicon of the same doping type as the bottom terminal. Following formation of the epitaxial silicon stack, at least a portion of the mask is removed to expose portions of the top terminal, channel, and bottom terminal. Next, a gate dielectric layer is formed on the exposed portions of the top terminal, channel, and bottom terminal. A gate is then formed in contact with the gate dielectric layer such that the gate is positioned adjacent the channel and adjacent at least a portion of the bottom terminal and the top terminal.
Preferably, formation of the epitaxial silicon stack comprises the following steps. First, a bottom silicon layer is grown on the substrate surface and is simultaneously doped to form the bottom terminal. Next, a channel silicon layer is grown on the bottom terminal and is simultaneously doped to form the channel. Following formation of the channel, a top silicon layer is grown on the channel and is simultaneously doped to form the top terminal.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.
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C. Y. Chang and S. M. Sze,U
Emmi Peter A.
Park Byeongju
International Business Machines - Corporation
Le Dung Ans
Nelms David
Ratner & Prestia
Townsend, Esq. Tiffany L.
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