Vertical bloch line memory

Details Vertical bloch line memory Vertical bloch line memory

1992-06-29

1995-07-25

Yoo, Do Hyun

Static information storage and retrieval

Magnetic bubbles

Strip domain

365 87, G11C 1908

Patent

active

054368618

ABSTRACT:
A new read gate design for the vertical Bloch line (VBL) memory is disclosed which offers larger operating margin than the existing read gate designs. In the existing read gate designs, a current is applied to all the stripes. The stripes that contain a VBL pair are chopped, while the stripes that do not contain a VBL pair are not chopped. The information is then detected by inspecting the presence or absence of the bubble. The margin of the chopping current amplitude is very small, and sometimes non-existent. A new method of reading Vertical Bloch Line memory is also disclosed. Instead of using the wall chirality to separate the two binary states, the spatial deflection of the stripe head is used. Also disclosed herein is a compact memory which uses vertical Bloch line (VBL) memory technology for providing data storage. A three-dimensional arrangement in the form of stacks of VBL memory layers is used to achieve high volumetric storage density. High data transfer rate is achieved by operating all the layers in parallel. Using Hall effect sensing, and optical sensing via the Faraday effect to access the data from within the three-dimensional packages, an even higher data transfer rate can be achieved due to parallel operation within each layer.

REFERENCES:
patent: 4122538 (1978-10-01), Lins
patent: 5031140 (1991-07-01), Hidaka
patent: 5105383 (1992-04-01), Saito et al.
Vertical Bloch Line Memory by R. R. Katti, J. C. Wu and H. L. Stadler; 1990 NASA Space Engineering Research Center--Symposium on VLSI Design, pp. 8.3.1 to 8.3.20.
Integrated Vertical Bloch Line Memory by R. R. Katti, J. C. Wu and H. L. Stadler; 1990 NASA Technology 2000 Conference Proceedings, pp. 25-33.
Design and Characteristics for Vertical Bloch Line Memory Using Ring-Shaped Domain by H. Matsutera, K. Mizuno and Y. Hidaka; IEEE Transactions on Magnetics, vol. Mag-23, No. 5, Sep. 1987, pp. 2320-2325.
Operation of a VBL Memory Write Gate by J. C. Wu and F. B. Humphrey; IEEE Transactions on Magnetics, vol. Mag-21, No. 5, Sep. 1985, pp. 1773-1775.
Chip Organization of Bloch Line Memory by T. Suzuki, H. Asada, K. Matsuyama, E. Fujita, Y. Saegusa, K. Morikawa, K. Fujimoto, M. Shigenobu, K. Nakashi, H. Takamatsu, Y. Hidaka, and S. Konishi; IEEE Transactions on Magnetics, vol. Mag-22, No. 5, Sep. 1986, pp. 784-789.
Vertical Bloch Line Memory by F. B. Humphrey and J. C. Wu; IEEE Transactions on Magnetics, vol. Mag-21, No. 5, Sep. 1985, pp. 1762-1766.

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