Vertical bipolar transistor with a majority carrier...

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means

Reexamination Certificate

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Details

C257S347000, C257S350000, C257S370000, C257S565000, C257S592000

Reexamination Certificate

active

07115965

ABSTRACT:
The present invention provides a “subcollector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped subcollector. Instead, the inventive vertical SOI BJT uses a back gate-induced, majority carrier accumulation layer as the subcollector when it operates. The SOI substrate is biased such that the accumulation layer is formed at the bottom of the first semiconductor layer. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS. A back-gated CMOS device is also provided.

REFERENCES:
patent: 5627401 (1997-05-01), Yallup
patent: 6538916 (2003-03-01), Ohsawa

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