Vertical bipolar transistor formed using CMOS processes

Details Vertical bipolar transistor formed using CMOS processes Vertical bipolar transistor formed using CMOS processes

2001-11-30

2003-11-18

Wojciechowicz, Edward (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S371000, C257S373000, C257S375000, C438S154000, C438S199000, C438S514000

Reexamination Certificate

active

06649983

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates in general to the field of integrated electronic systems and more particularly to the architecture and formation of a vertical bipolar transistor constructed using adjunct CMOS processes.
BACKGROUND OF THE INVENTION
The construction of field effect devices in CMOS technologies involves the use of sequential implant processes to form conductive and semiconductive regions within the outer surface of a semiconductor substrate. These implant processes are optimized to enable the field effect devices to function in complimentary fashion. P-channel devices and n-channel devices are formed on the same substrate using photolithographic processes to cover certain of the devices while implant processes are performed on the remaining devices.
State of the art bipolar transistors require different implant and photolithographic masking processes. Many integrated architectures require or may be optimized if the integrated system can utilize both field effect and bipolar devices on the same integrated substrate. Unfortunately, the use of implant processes to form field effect devices and then subsequent different implant processes to form bipolar devices greatly increases the cost and complexity of the formation of the device. As such, designers have attempted to use the same implant processes for the field effect devices to create various bipolar structures within the integrated system. These techniques have been somewhat successful but have not utilized all of the potential implant regions possible with typical CMOS processing.
For example, U.S. Pat. No. 6,303,420 discloses a technique of using a pocket implant to form a base region of a bipolar transistor which utilizes the substrate as the collector. However, this technique is limited in its effectiveness because the formation of the emitter of the device must be extremely shallow to prevent eradication of the base region formed by the pocket implant. This shallow emitter dictates that the device must be masked from subsequent surface silicidation steps and that direct vertical contact to the emitter is not possible. In order to solve these problems, additional masking and horizontal contact coupling regions must be added which greatly increase the cost and complexity of the device.
SUMMARY OF THE INVENTION
Accordingly, a need has arisen for a new architecture and techniques for forming a bipolar transistor using the operations used to form CMOS devices in an integrated semiconductor system.
In accordance with the teachings of the present invention, integrated device architectures are provided herein that include vertical bipolar transistors formed using implant steps associated with the formation of adjunct CMOS devices. These techniques substantially reduce or eliminate problems associated with prior device architectures and formation techniques.
In accordance with one embodiment of the present invention, a pnp bipolar device is formed in parallel with an nMOS field effect device and a pMOS field effect device on a p-type semiconductor substrate. A p-type source drain implant is used to form the source and drain for the pMOS field effect device and an emitter of a vertical bipolar device. A n-type pocket implant is used to dope the channel of the pMOS field effect device and is also used to form the base region of the vertical bipolar device. A n-type implant process is used to form the source drain regions of nMOS field effect devices and is also used to form a base contact region for the base region of the vertical bipolar device. A p-type implant is used to form a p-type well region associated with nMOS field effect devices and is also used to form a collector coupling region of the vertical bipolar device. The p-type source drain implant is also used to form a collector contact region of the vertical bipolar device. A region of the p-type substrate forms the collector region of the pnp device. While bipolar pnp transistors which utilize the substrate as the collector can always be formed using adjunct CMOS processes by using the implanted n-well as the base region, by using an n-type pocket implant or an n-type high voltage drain extension implant to form the base region, the base region comprises a much lower Gummel number thereby increasing the h
fe
or current gain of the device.
An important technical advantage of the present invention inheres in the fact that implant processes which are used to form field effect devices on an integrated substrate can also be used to form vertical bipolar devices on the same substrate. In this manner, bipolar transistors can be used with both pMOS and nMOS field effect devices to create complex BiCMOS circuitry and bandgap reference circuits without incurring the complexity and costs associated with conventional techniques for forming these structures.


REFERENCES:
patent: 6303420 (2001-10-01), Sridhar et al.

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