Vertical bipolar SRAM cell, array and system, and a method of ma

Details Vertical bipolar SRAM cell, array and system, and a method of ma Vertical bipolar SRAM cell, array and system, and a method of ma

1997-06-02

1999-04-20

Nguyen, Viet Q.

Static information storage and retrieval

Systems using particular element

Semiconductive

365188, 257552, 257556, 257566, 257577, H01L 2704

Patent

active

058963138

ABSTRACT:
An SRAM memory cell is provided in which a pair of cross-coupled n-type MOS pull-down transistors are coupled to respective parasitically formed bipolar pull-up transistors. The memory cell is formed within a semiconductor layer which extends over a buried layer. The bipolar transistors are formed parasitically from the buried layer and the semiconductor layer used to form the pull-down transistors. The bases of the bipolar transistors may also be dynamically controlled. An SRAM memory array having a plurality of such memory cells and a computer system incorporating the SRAM memory array are also provided.

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patent: 5483483 (1996-01-01), Choi et al.
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patent: 5594261 (1997-01-01), Temple
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Analysis and Design of Digital Integrated Circuits, 2.sup.ND Edition, by David Hodges, pp. 364-368, 1988

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