Vertical bipolar SRAM cell, array and system, and a method for m

Details Vertical bipolar SRAM cell, array and system, and a method for m Vertical bipolar SRAM cell, array and system, and a method for m

1998-04-30

1999-05-25

Fears, Terrell W.

Static information storage and retrieval

Systems using particular element

Semiconductive

36518901, G11C 1300

Patent

active

059075031

ABSTRACT:
An SRAM memory cell is provided in which a pair of cross-coupled n-type MOS pull-down transistors are coupled to respective parasitically formed bipolar pull-up transistors. The memory cell is formed within a semiconductor layer which extends over a buried layer. The bipolar transistors are formed parasitically from the buried layer and the semiconductor layer used to form the pull-down transistors. The bases of the bipolar transistors may also be dynamically controlled. An SRAM memory array having a plurality of such memory cells and a computer system incorporating the SRAM memory array are also provided.

REFERENCES:
patent: 5453636 (1995-09-01), Eitan et al.
patent: 5594261 (1997-01-01), Temple
patent: 5594265 (1997-01-01), Shimizu et al.
patent: 5594683 (1997-01-01), Chen et al.
Analysis and Design of Digital Integrated Circuits, 2.sup.nd Edition, by David Hodges, pp. 364-368, 1988.

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