Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-04-01
2004-05-18
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S672000, C438S687000, C438S926000
Reexamination Certificate
active
06737351
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates in general to the fabrication and operation of semiconductor devices and, more particularly, to apparatus and methods for diffusion limiting voids formed in semiconductor device structures during fabrication and operation of the semiconductor device.
BACKGROUND OF THE INVENTION
The continual demand for enhanced integrated circuit performance has resulted in, among other things, a dramatic reduction of semiconductor device geometries, and continual efforts to optimize the performance of every sub-structure within a semiconductor device. A number of improvements and innovations in fabrication processes, material composition, and layout of the active circuit levels of semiconductor devices have resulted in very high-density circuit designs. Increasingly dense circuit design has, consequently, greatly improved a number of performance issues—such as minimizing signal propagation delays through the active circuit levels of semiconductor devices.
Only recently, however, have other layers and structures within semiconductor devices received such scrutiny and been the subject of optimization efforts. For many years, most semiconductor devices utilized “back-end” (e.g., metal interconnect and dielectric) layers based on very mature aluminum (Al) and silicon dioxide (SiO
2
) technology. With the improvements in the active circuit levels, it was not uncommon for 50% or more of propagation delays to occur in the back-end layers, in semiconductor devices utilizing such mature back-end technologies. As a result, a large segment of semiconductor manufacturing is transitioning from the mature Al-based back-end materials and technologies to new, alternative materials and technologies. With that transition a number of new and unexpected challenges and problems arise—some of which are counter-intuitive based on an understanding of the mature back-end materials and technologies.
SUMMARY OF THE INVENTION
Among the new, alternative technologies being utilized, copper (Cu) and copper-based materials and technologies are gaining acceptance and preference for use in semiconductor device back-ends. Copper's relatively low resistivity and high melting point make it a particularly attractive metallization choice for high performance semiconductor devices. Using copper in semiconductor back-ends reduces path resistance, thus decreasing signal propagation delays. A low-K dielectric may be utilized in conjunction with copper metallization, further decreasing signal propagation delays through the back-end.
Because the use of copper based back-ends in semiconductor processing is still relatively immature, a number of physical properties and behaviors of copper, and the effects of those properties and behaviors on the performance of semiconductor devices, have yet to be fully comprehended. One such problem that has become prevalent in devices utilizing such back-end technologies is the formation of stress-induced voids (SIVs) around via structures—particularly vias that are relatively isolated and located in proximity to relatively wide metallic interconnects. The formation of such voids can destroy electrical conductivity in a device and present numerous and catastrophic device reliability problems.
Previously, the older, Al-based technologies often experienced very different void problems. Such problems were most prevalent in relatively narrow metallic interconnects. Voids would form in grain boundaries along the length of the interconnect and, if significant in size, would either partially or completely sever the continuity of the interconnect, causing an open in the device circuitry. Voiding around via structures, for most device applications, was not prevalent. Thus, previously developed methods of addressing void problems generally do not comprehend void formation around via structures in proximity to wide metallic interconnects. Those conventional methods were tailored toward dealing with voids along the span of very narrow metallic interconnects. Furthermore, such conventional methods are often rendered inefficient or impracticable with the use of copper and other new back-end design materials and processes.
Even designs currently utilizing copper and other new back-end materials and processes appear to address SIV problems in only an ad-hoc fashion. SIV problems do not appear to be addressed in a systematic fashion—they are dealt with only after they have resulted in reliability problems. Often, the problematic device is merely re-fabricated several times until a device without problems is yielded. Or, sometimes, individual device features are manually adjusted and the device re-processed. Obviously, such approaches are inefficient from cycle time and cost perspectives.
The present invention recognizes that a primary cause of SIVs is the diffusive migration of vacancies from the grain boundaries, interfaces, surfaces, lattice, or lattice interstices of the metal interconnect toward via structures. The present invention further recognizes that a number of stress gradients inherent in the fabrication and operation of such semiconductor devices promote and accelerate the diffusive migration of such vacancies toward via structures. Therefore, a versatile system for limiting the diffusive formation of stress-induced voids in semiconductor interconnect structures in a cost-effective and efficient manner is now needed; providing for consistent and scalable device design and fabrication, and for improved device performance and reliability, while overcoming the aforementioned limitations of conventional methods.
The present invention provides a system that substantially minimizes, and potentially eliminates, the effects of stress-induced voiding in dual-damascene structures. The present invention provides a system that addresses such effects from a structural perspective, a performance perspective, and a combined structural/performance perspective. In one embodiment of the present invention, the negative effects of SIV on device performance are mitigated through electrical redundancy. In another embodiment of the present invention, the negative effects of SIV are mitigated through diffusive buffers. In yet another embodiment of the present invention, electrical redundancy is employed in conjunction with diffusive buffering.
The present invention provides a system for producing semiconductor devices to decrease diffusive damage effects to a particular structure of concern (i.e., a primary structure). An active diffusion volume, within which the primary structure is located, is determined. Then, a buffer structure, adapted to share a select redundancy characteristic with the primary structure, is disposed within the active diffusion volume.
The present invention also provides a system for producing a semiconductor device having a copper-based, dual-damascene structure. An active diffusion volume, within which the dual-damascene structure is located, is determined. Then, a buffer structure, adapted to share a select redundancy characteristic with the dual-damascene structure, is disposed within the active diffusion volume.
The present invention further provides a system for semiconductor device structures comprising a first metallic interconnect, a second metallic interconnect, and a primary via structure, disposed between and electrically intercoupling the first and second metallic interconnects. A buffer structure is disposed upon the first metallic interconnect in proximity to the primary via structure, and adapted to buffer the primary via structure from diffusive voiding occurring at a contact point between the primary via structure and the first metallic interconnect.
REFERENCES:
patent: 6121156 (2000-09-01), Shamble et al.
patent: 6258707 (2001-07-01), Uzoh
patent: 6352917 (2002-03-01), Gupta et al.
patent: 6368967 (2002-04-01), Besser
McPherson Joe W.
Ogawa Ennis T.
Estrada Michelle
Fourson George
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Wade James Brady III
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