Versatile logic element and logic array block

Details Versatile logic element and logic array block Versatile logic element and logic array block

2005-08-30

2005-08-30

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S039000, C326S041000

Reexamination Certificate

active

06937064

ABSTRACT:
An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an “add-or-subtract control signal” that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.

REFERENCES:
patent: 4706216 (1987-11-01), Carter
patent: 4758985 (1988-07-01), Carter
patent: 5260610 (1993-11-01), Pedersen et al.
patent: 5331226 (1994-07-01), Goetting
patent: 5352940 (1994-10-01), Watson
patent: 5399922 (1995-03-01), Kiani et al.
patent: 5438295 (1995-08-01), Reddy et al.
patent: 5488316 (1996-01-01), Freeman et al.
patent: 5689195 (1997-11-01), Cliff et al.
patent: 5815003 (1998-09-01), Pedersen
patent: 5821773 (1998-10-01), Norman et al.
patent: 5831448 (1998-11-01), Kean
patent: 5835998 (1998-11-01), Pedersen
patent: 5920202 (1999-07-01), Young et al.
patent: 5923185 (1999-07-01), Zhou
patent: 5953537 (1999-09-01), Balicki et al.
patent: 5999015 (1999-12-01), Cliff et al.
patent: 5999016 (1999-12-01), McClintock et al.
patent: 6020756 (2000-02-01), New
patent: 6034540 (2000-03-01), Mendel
patent: 6051992 (2000-04-01), Young et al.
patent: 6066960 (2000-05-01), Pedersen
patent: 6069487 (2000-05-01), Lane et al.
patent: 6084427 (2000-07-01), Lee et al.
patent: 6107822 (2000-08-01), Mendel et al.
patent: 6118300 (2000-09-01), Wittig et al.
patent: 6122720 (2000-09-01), Cliff
patent: 6124731 (2000-09-01), Young et al.
patent: 6167558 (2000-12-01), Trimberger
patent: 6184707 (2001-02-01), Norman et al.
patent: 6191610 (2001-02-01), Wittig et al.
patent: 6201410 (2001-03-01), New et al.
patent: 6211696 (2001-04-01), Skahill et al.
patent: 6249149 (2001-06-01), Pedersen
patent: 6255846 (2001-07-01), Lee et al.
patent: 6271680 (2001-08-01), Mendel et al.
patent: 6275065 (2001-08-01), Mendel
patent: 6323677 (2001-11-01), Lane et al.
patent: 6323682 (2001-11-01), Bauer et al.
patent: 6362648 (2002-03-01), New et al.
patent: 6400180 (2002-06-01), Wittig et al.

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