Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-03-05
2002-03-12
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S624000, C438S625000, C438S626000, C438S627000, C438S629000, C438S631000, C438S633000, C438S637000, C438S638000, C438S666000, C438S669000, C438S672000, C438S675000
Reexamination Certificate
active
06355563
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a method of metallization in the fabrication of integrated circuits, and more particularly, to a method of integrating low dielectric constant materials with copper metallization in the manufacture of integrated circuits.
(2) Description of the Prior Art
Copper metallization has become a future trend in integrated circuit manufacturing. However, copper contamination of the intermetal dielectric layer is a problem, especially for the desirable low dielectric constant (low-k) materials. Copper mobile ion contamination is fatal and detrimental to low-k dielectric materials. In addition, low-k dielectrics are also fairly susceptible to the harsh effects of plasma ashing as well as plasma etching. It is desired to provide a smooth integration of low-k dielectric materials with copper metallization in order to attain a device of high performance quality.
Co-pending U.S. patent application Ser. No. 09/398,294 (CS-99-024) to L. J. Xun et al, filed on Sept. 20, 1999, teaches using a dielectric layer to protect an underlying low-k dielectric during plasma ashing. U.S. Pat. No. 6,001,730 to Farkas et al and U.S. Pat. No. 5,723,387 to Chen disclose copper dual damascene processes. U.S. Pat. No. 6,033,963 to Huang et al teaches forming a metal gate using a replacement gate process.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of copper metallization in the fabrication of integrated circuit devices.
Another object of the present invention is to provide an effective and very manufacturable method of integrating low dielectric constant materials with copper metallization in the fabrication of integrated circuit devices.
Another object of the invention is to prevent copper contamination of the low-k dielectric layer.
Yet another object of the invention is to protect the low-k dielectric layer from damage caused by plasma etching and/or plasma ashing.
A further object of the invention is to effectively integrate low-k dielectrics with copper metallization using a replacement line and replacement via technique.
A still further object of the invention is to prevent copper mobile ion contamination of the low-k dielectric layer with a sidewall liner layer.
Another further object of the invention is to protect the low-k dielectric layer from plasma etch and ashing damage by electron-beam, ion-beam, or X-ray curing.
Yet another object of the invention is to effectively integrate low-k dielectric with copper metallization using replacement line and replacement via techniques which are applicable to single, double, and triple damascene processes.
In accordance with the objects of this invention a new method to integrate low dielectric constant dielectric materials with copper metallization is achieved. A metal line is provided overlying a semiconductor substrate and having a nitride capping layer thereover. A polysilicon layer is deposited over the nitride layer and patterned to form dummy vias. A dielectric liner layer is conformally deposited overlying the nitride layer and dummy vias. A dielectric layer having a low dielectric constant is spun-on overlying the liner layer and covering the dummy vias. The dielectric layer is polished down whereby the dummy vias are exposed. Thereafter, the dielectric layer is cured whereby a cross-linked surface layer is formed. The dummy vias are removed thereby exposing a portion of the nitride layer within the via openings. The exposed nitride layer is removed. The via openings are filled with a copper layer which is planarized to complete copper metallization in the fabrication of an integrated circuit device.
REFERENCES:
patent: 5663108 (1997-09-01), Lin
patent: 5723387 (1998-03-01), Chen
patent: 5801093 (1998-09-01), Lin
patent: 5811352 (1998-09-01), Numata et al.
patent: 5861673 (1999-01-01), Yoo et al.
patent: 5880018 (1999-03-01), Boeck et al.
patent: 5888897 (1999-03-01), Liang
patent: 5930672 (1999-07-01), Yamamoto
patent: 6001730 (1999-12-01), Farkas et al.
patent: 6010955 (2000-01-01), Hashimoto
patent: 6030896 (2000-02-01), Brown
patent: 6033963 (2000-03-01), Huang et al.
patent: 6033977 (2000-03-01), Gutsche et al.
patent: 6037216 (2000-03-01), Liu et al.
patent: 6117766 (2000-09-01), Yoon et al.
patent: 6140238 (2000-10-01), Kitch
patent: 6143641 (2000-11-01), Kitch
patent: 6168985 (2001-01-01), Asano et al.
patent: 2001/0005627 (2001-06-01), Matsubara
Cha Randall Cher Liang
Chan Lap
Lee Tae Jong
Lim Yeow Kheng
See Alex
Chartered Semiconductor Manufacturing Ltd.
Gurley Lynne
Pike Rosemary L. S.
Saile George O.
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