Verifying dynamic memory refresh

Details Verifying dynamic memory refresh Verifying dynamic memory refresh

1993-06-29

1994-08-02

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Data refresh

365201, 3652335, 36518902, G11C 700

Patent

active

053352025

ABSTRACT:
A dynamic memory having self refreshing capability performed without external strobing, is interruptable and can be strobed to initiate a refresh cycle for testing interrupt response timing. In operation of such a dynamic memory, interruption of a self refresh cycle precedes initiation of a read or write cycle by a time t.sub.RPS, sufficient for row precharge. Although t.sub.RPS can be estimated based on worst case analysis, lower t.sub.RPS characteristics can be guaranteed, resulting in higher yields, by measuring t.sub.RPS during memory fabrication using circuits and methods disclosed. In an alternate embodiment, output of a signal indicative of the beginning of a refresh cycle is enabled by a test signal.

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patent: 5208779 (1993-05-01), Walther et al.
patent: 5229969 (1993-07-01), Lee et al.

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