Verification supporting system

Details Verification supporting system Verification supporting system

2011-07-19

2011-07-19

Rossoshek, Helen (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Logic design processing

C716S104000, C716S107000, C716S111000, C716S132000, C716S136000, C703S013000, C703S014000

Reexamination Certificate

active

07984403

ABSTRACT:
A verification target register to be verified is specified from a configuration of a verification target circuit, and patterns requiring verification are extracted as a coverage standard with regard to the specified verification target register. When the patterns are extracted, a DIRW matrix is prepared to indicate possibly occurring state transitions among four states Declare, Initialize, Read, and Write in the register included in the verification target circuit, and used to decide two coverage standards, a matrix coverage standard and an implementation coverage standard.

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